Variation-Aware Test for Nanoscale CMOS Integrated Circuits

Semiconductor manufacturing test is affected by fabrication process and power supply voltage (PV) variation as demonstrated recently by the investigating team. Performing test using existing methods and without considering PV variation will lead to defects being missed by during test leading to reduced yield and reliability of integrated circuits. This grant application is focused on exploring and developing new and efficient test methods capable of mitigating the impact of PV variation leading to improved test quality and higher dependability. This project will provide significant advances in the present state-of-the-art semiconductor test and will help to establish the scientific foundation required for the development of next generation PV variation-aware test methods and tools for nanoscale integrated circuits. This includes new fault models for resistive open and resistive short defects that capture PV variation; accurate metrics for assessing and quantifying the impact of such variation on the quality and cost of test, and two variation-aware test pattern generation methods (logic and delay) capable of mitigating test escapes due to PV variation and efficient in terms of defect coverage and volume of test data. The developed models, metrics, and test generation methods will be evaluated using comprehensive simulation with nano-meter synthesized benchmark circuits and real-life test problem provided by the project industrial partner. This is a three-year project involving one named post doctoral researcher and one PhD student. The project will be carried out in collaboration with ARM (Cambridge) and Synopsys (US), and in collaboration with Prof. K. Chakrabarty (Duke Uni.), and Prof. S. Kundu (Uni. of Massachusetts) as visiting researchers. The research we propose is aligned with the EPSRC signposted Grand Challenges in microelectronics design as identified by the EPSRC network grant Developing a Common Vision for UK Research in Microelectronic Design . This proposal is aligned in particular with GC3 (More for Less: Performance-driven design for next generation chip technology), where one of the main technical issues that need to be addressed in this GC is Test and Verification if the semiconductor industry is to continue to produce more efficient designs with better performance, lower power and lower test and verification cost.