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Computer Architecture

When you'll study it
Semester 2
CATS points
15
ECTS points
7.5
Level
Level 5
Module lead
Mark Zwolinski
Academic year
2026-27

Module overview

This course ensures that students both understand how a CPU works, but are also able to implement a working CPU. The course covers basic data- and control-path design, as well as how to implement a working CPU for an existing ISA in RTL. Standard optimisations (pipelining and caches) are introduced to explain basic techniques for improving performance. The course positions the CPU as one component within a larger computational system, and considers how CPUs are integrated with other devices within a modern SoC context.