SCN3ME: Scalable CMOS N-well, 3 metal, non-silicided, high resistance layer available. Adds a second polysilicon layer (poly2) as the upper electrode of a poly capacitor.
SCN3ME_SUBM: Uses revised layout rules for better fit to sub-micron processes (see MOSIS Scalable CMOS (SCMOS) Design Rules.
Fabricated on AMI 0.50 micron process runs.
Masks required for analogue designs (POLY2, HI_RES_IMPLANT and POLY2_CONTACT) have been omitted from the following list.
Layer GDS CIF CIF Synonym Rule
SectionNotes N_WELL 42 CWN 1 ACTIVE 43 CAA 2
POLY 46 CPG 3
N_PLUS_SELECT 45 CSN 4
P_PLUS_SELECT 44 CSP 4
CONTACT 25 CCC CCG 5, 6 POLY_CONTACT 47 CCP 5 Can be replaced by CONTACT ACTIVE_CONTACT 48 CCA 6 Can be replaced by CONTACT METAL1 49 CM1 CMF 7
VIA 50 CV1 CVA 8
METAL2 51 CM2 CMS 9
VIA2 61 CV2 CVS 14 METAL3 62 CM3 CMT 15 GLASS 52 COG 10
PADS 26 XP
Non-fab layer used to highlight pads Comments -- CX Comments
In addition to these mask rules, Minimum Density Rules and Process-Induced Damage Rules must be considered.
MOSIS Scalable design rules require that layout is on a 1/2 lambda grid.