Register Balancing

• Register balancing is a very useful command when it comes to optimizing designs that are made up of pipelines.

• The concept here is to allow Design Compiler to move logic from one stage of the pipeline to another. This would allow Design Compiler the flexibility to move logic away from pipeline stages that are overly constrained to pipeline stages that have additional timing.

• You can balance the register after you compile by typing:

• balance_registers