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Table of contents

Author: Iain McNally

RTL Synthesis using Design Compiler Learning Outcomes: Digital Design Flow Design Compiler Lab Instructions Synthesis Process Slide 6 Design Directory Management How to setup Linux Environment to run DC Slide 9 2. Read in the HDL Slide 11 3. Elaboration Slide 13 Add Constraints Add Constraints: Defining the clock Add Constraints: Optimize Area Slide 17 Slide 18 4. Synthesis Slide 20 Design Analysis Design Analysis: Power Report Slide 23 Design Analysis: Timing Slide 25 Slide 26 Slide 27 Design Analysis: Save Reports Slide 29 Timing Optimization Slide 31 Fix Naming Save Out the Design: The easy way…. Using Design Vision Simple Script How to get Help: Discussion Points Appendix 1: Optimization using synthesis tool Compilation with map_effort high option Register Balancing Removing Hierarchy Slide 43 Choosing High-Speed Implementation for High-level Functional Module Slide 45 How to Fix Hold Time Violation How Fix Hold Time Violation Slide 48