How Fix Hold Time Violation

• During synthesis design, the designer can set the attribute set_fix_hold to have Design Compiler fix the hold violations using the following commands:

• set_fix_hold <clock_name>

• compile –map_effort high -incremental_mapping

• Example: the following command sets a fix_hold attribute on clock "clk1".

• set_fix_hold clk1

• To remove the fix_hold attribute from clock "clk1“:

• remove_attribute [get_clocks clk1] fix_hold