Simple Script

• analyze -format verilog “qmults.sv wrap_qmults.sv”

• elaborate wrap_qmults

• create_clock –name master_clock -period 6 [get_ports Clock]

• compile

• report_area > synth_area.rpt

• report_power > synth_power.rpt

• change_names -rules verilog -hierarchy -verbose

• write -f verilog -hierarchy -output “qmults_syn.v"

• write_sdc design.sdc

• write_sdf design.sdf

• exit