Save Out the Design:

• This is the final step in the synthesis flow, it allows the designer to transfer the synthesised circuit to the next stage of the design flow. This can be done as follows:

• 1. For Place and Route Stage: You need to save the following files:

• 1.1. Save the hierarchical Verilog:

• write -f verilog -hierarchy -output “qmults_syn.v"

• 1.2. Save the timing constraints (sdc file)

• write_sdc design.sdc

• 2. For post synthesis simulation: You need to save the following files:

• 1.1. Save the hierarchical Verilog:

• write -f verilog -hierarchy -output “qmults_syn.v"

• 1.2. Save the timing information (sdf file)

• write_sdf design.sdf