Integrated Circuit Engineering 2

UoC Tiny Chip

Introduction

The University of Canterbury Tiny Chip has been designed to support student design projects on the Integrated Circuit Engineering 2 course (ENEL435).

The main features of the UoC Tiny Chip are:

An outline of the frame is shown below:

Frame

A more detailed view of the connections for one of the student designs is shown below:

DES1

When testing the DES1 design, S1:S0 will be set to "01" thereby disabling all transmission gates for the other three designs. Power will be supplied to the pad ring via VDD and to the DES1 core via Vdd1. All other core power pins (Vdd0 Vdd2 Vdd3) will be grounded. The result is that DES1 is isolated from the problems of other student designs on the same chip including port to port and even power to ground shorts.

Tanner L-Edit and S-Edit Libraries

Configuration

Configuration is performed via the genUoCframe command acting on a specification file. Configuration may be considered as a two stage process (although both stages can be completed simultaneously). These stages are selection of pinout and selection of designs:

  1. Selection of Pinout

    The task is to decide which pins on the final chip will be inputs and which will be outputs. In each case allocating a name to the chosen pin. Taking a very simple example in which the student task is to design a two input NAND gate, the following specification would suffice: 

        pinout NAND
      1 Input A
      2 Input B
      3 Output Y
    end pinout
    Here pins 1 and 2 are declared as inputs with names A and B, while pin 3 is defined as an output named Y. The pinout as a whole is given the name "NAND".

    Remember when creating your own pinouts that the following pins are pre-defined: 6, 10, 11, 20, 29, 30, 35 & 40.

    Assuming that this file where saved on Sun Unix machine as spec_ex1, the configuration is performed by typing: 

        genUoCframe < spec_ex1

    The output from this configuration process is a device pinout file, NAND.dev which is used by the TesterGen software and the TestosterICs Functional Tester. If you examine this file you will see that unconfigured pins retain their default names (Pad_4, Pad_5, Pad_7 .. Pad_39) and are all defined as inputs.

    In addition to this device pinout file, the pinout information should also be used to create a template design for the students. This template or base design contains the ports needed for connection of the student design into the frame:

    Base Design

    Note that the unused ports (Pad_4, Pad_5, Pad_7 .. Pad_39) must exist on the final student design and must not be shorted to any other node since they will be connected to input pads in the frame.

    A modified specification file, spec_ex2, will create a base design named MY_DESIGN with the correct pinout information: 

        pinout NAND
      1 Input A
      2 Input B
      3 Output Y
    end pinout
    basedesign MY_DESIGN

    Note that there must be no blank lines in the specification file since a blank line terminates the genUoCframe configuration script. Note also that the existing documentation tells the students that the base design will be called MY_DESIGN so it is probably best not to change this name. As before configuration is performed by typing: 

        genUoCframe < spec_ex2

    The files created are NAND.dev (as before) plus MY_DESIGN.mag and MY_DESIGN.gds.

    MY_DESIGN.mag is a magic file which can be viewed if you are running eXcursion in full 8-bit mode (i.e. the MS Windows display must be configured in 256 colour mode) using the command: 

        ex8magic7 MY_DESIGN

    MY_DESIGN.gds is a GDS II format file exported from magic, suitable for import to L-Edit.

    Creating a new Initial Cell Library

    Having created a GDS II file containing the MY_DESIGN cell you will need to build it into an initial cell library to give to the students:

    In order to create the corresponding S-Edit file you will have to edit the MY_DESIGN cell in the existing MY_DESIGN.sdb file by hand. Remember to change the schematic and symbol views to suit the new pinout information.

    Although example versions of these files are stored in W:\TannerLibs\mAMIs\EXLIBS2003\, New versions should be stored in W:\TannerLibs\mAMIs\ which is where existing documentation suggests that they will be found.

  2. Selection of Student Designs

    The task is to allocate student designs to their final locations on one or more chips to be fabricated.

    Assuming that you have 7 teams AAA, BBB, CCC, DDD, EEE, FFF & GGG each team having provided a toplevel cell with a name of the form XXX_DESIGN (where XXX is their team identifier), you may allocate the first four teams to CHIP1. A new specification file, spec_ex3, will create a frame for CHIP1 which includes the designs as required: 

        pinout NAND
      1 Input A
      2 Input B
      3 Output Y
    end pinout
    basedesign MY_DESIGN
    frame CHIP1
      0 AAA_DESIGN
      1 BBB_DESIGN
      2 CCC_DESIGN
      3 DDD_DESIGN
    end frame

    The files created are NAND.dev, MY_DESIGN.mag, MY_DESIGN.gds (as before) plus CHIP1.mag and CHIP1.gds.

    In each case the design will be correctly placed and correctly orientated (with CCC_DESIGN and DDD_DESIGN upside down) provided that the students haven't moved the ports. It would be good to develop a method for the students to check that they have not moved the ports or the bounding box for their designs as this would significantly reduce supervisor workload at handin time.

    To complete the task we need to define a second chip, CHIP2, which includes the other 3 designs. In spec_ex4 below, we leave the DES3 position empty but it would also be possible to include a supervisor design in this space or to duplicate one of the student designs (maybe the best design from the other chip): 

        pinout NAND
      1 Input A
      2 Input B
      3 Output Y
    end pinout
    basedesign MY_DESIGN
    frame CHIP1
      0 AAA_DESIGN
      1 BBB_DESIGN
      2 CCC_DESIGN
      3 DDD_DESIGN
    end frame
    frame CHIP2
      0 EEE_DESIGN
      1 FFF_DESIGN
      2 GGG_DESIGN
    end frame

    The files created are NAND.dev, MY_DESIGN.mag, MY_DESIGN.gds, CHIP1.mag, CHIP1.gds, CHIP2.mag and CHIP2.gds.

    Creating Chip Files for Fabrication

    Here we want to merge the new toplevel cell (e.g. CHIP1) with the pad cells, the frame cells and the student designs.

    By default each chip will be saved in a new L-Edit file although it would be possible to subsequently merge all chips into a single file before fabrication if this was desired.

Iain McNally

9-6-2003