Create a full mask level design for a 2 input NOR gate based on the stick diagram shown here:
This assignment is based on question 2 from the 2006/2007 exam paper.
This assignment is marked automatically and instantly on submission.
CIF format
The submitted file must be in CIF format. CIF is a file format used to transfer IC design files to foundries for fabrication. It is also useful to transfer designs between different CAD tools. To convert your design to CIF format, find the "Export CIF" dialogue from the L-Edit "File" menu.
File -> Export Mask Data -> CIF...
C-Bass submission
Submission of files is via the web based Computer-Based Assignment Submission System
Preparation for submission
In order for the automated feedback to work, your design must conform to a number of specifications:
Technology = ICD 0.3um CMOS (version 2)
The file submitted must be based on the icdc03a_tech.tdb L-Edit Technology Library. You should ensure that it passes all L-Edit Design Rule Check checks before submission.
Cell name = NOR2
The cell name within the L-Edit library must be NOR2. You should assume that cell names are potentially case sensitive and case insensitive. Thus you should expect the system to fail if you have named the cell nor2 (or Nor2) instead of NOR2. You should also expect the system to fail if your L-Edit file contains one cell named NOR2 and another named nor2 (or Nor2).
Port Names = A, B, Y, Vdd!, GND!
The port names should be exactly as shown on the stick diagram above, including the exclamation mark (which indicates a global signal name) and the case (note that GND! is all in upper case but Vdd! is mixed case).
PR Boundary Origin = (0,0)
The Place and Route Boundary is an imaginary rectangle around the cell which includes all the devices and interconnect (but not necessarily the whole of the N well and P+ implant masks). In order to use the cell in a larger design, L-Edit requires that the bottom left corner of the PR Boundary is at position (0,0) in the design.
Zero Width Ports on PR Boundary
When placing ports around the edge of the cell
(using the L-Edit place port tool),
you should ensure that the port rectangle that you draw has zero width
and aligns with the edge of the conductor and the PR Boundary.
The following figure shows a port label 'A' of zero width lining up
with the top of the polysilicon column:
Automated Feedback and Marking
The automated system will perform basic checks on the submitted CIF file and the convert the design to another CAD format (for the Magic VLSI editor) before performing more advanced checks.
Advanced checks are categorised and a mark will be assigned in each category. The categories include:
When looking at the detailed feedback, read it from the top down (there is no point in getting worried about simulation failure if you have warnings that your transistors are not well formed).
You may resubmit your work as many times as you like in order to improve your design (and your mark).
Once you are happy with your submitted design, you should use L-Edit's cross-section viewer tool and the process definition file icdc03a.xst to view cross-sections through the cell at various points (e.g. PMOS transistors, NMOS transistors, Vdd rail, GND rail).
Gaining an understanding of how masks relate to the three dimensional structure of your design is one of the most important aspects of this assignment.