Cadence Place & Route using AMS 0.35µm Libraries

(including pads,topcell=wrap_qmults)

Pre-requisites

This design flow expects that you are working in a design directory (e.g. ~/design/ams/ams_demo) with a number of sub-directories containing files created during the preceding synthesis stage:

• gate_level

  This directory contains a gate-level verilog netlist <topcell>.v (e.g. wrap_qmults.v) and an associated delay file <topcell>.sdf (e.g. wrap_qmults.sdf)

• constraints

  This directory contains a design constraints file <topcell>.sdc (e.g. wrap_qmults.sdc)

If your files aren't in these directories or don't have these names, then the first thing to do is to create any missing directories and copy the files into place with the correct names.

Preparation

Note - if you read the whole of the preparation section before typing any commands you may save yourself some time and some typing.

Within your working directory (e.g. ~/design/ams/ams_demo), create a new sub-directory for the place and route files and change to the new directory:

    mkdir place_and_route
    cd place_and_route

    ams_edis -tech c35 \
      -vn <topcell>.v -vt <topcell> \
      -metlay thin4M \
      -corelib CORELIB \
      -corevolt _3.3V \
      -corevolt_wc _3.3V \
      -corevolt_bc _3.3V \
      -iolib IOLIB \
      -iovolt _3.3V \
      -iovolt_wc _3.3V \
      -iovolt_bc _3.3V \
      -ediver EDI13.1ISR4

    ln -s ../../gate_level/<topcell>.v VERILOG/<topcell>.v
    ln -s ../../constraints/<topcell>.sdc CONSTRAINTS/<topcell>_func.sdc
    ln -s ../../constraints/<topcell>.sdc CONSTRAINTS/<topcell>_test.sdc

Note that the AMS scripts expect separate constraints files for functional mode (<topcell>_func.sdc) and test mode (<topcell>_test.sdc). This might allow us to specify tight timing constraints for the functional mode and looser constraints (e.g. a slower clock speed) for the test mode. For this walkthrogh we have generated only one set of timing constraints, so we link both of the expected files to the single constraints file (design.sdc).

Finally save a copy of the edi_custom_c35b4.tcl TCL script file into this directory.

If the source files are as specified in the prerequisites section above and you do not want to change any of the options to the ams_edis script, you can use the following sequence of commands in place of those above:

    prepare_edi <topcell> place_and_route
    cd place_and_route

Import the design

Within your new place and route directory (e.g. ~/design/ams/ams_demo/place_and_route), use the "encounter" command to start the place and route tool:

    encounter

You should see a new GUI window where you will later see the chip layout take shape. For now you should look at the terminal window where you should find the encounter prompt: "encounter 1>". Here you should type the following sequence of commands to import the design:

• Initialise the database (load in the design)

      amsDbSetup
  

• If your design supports one, specify a scan chain based on the scan data in and scan data out ports
  e.g.

      specifyScanChain ScanChain0 -start SDI -stop SDO
  

• Setup timing

      amsSetMMMC
      amsSetAnalysisView minmax {func test}
  

Note that commands in the list above which start with "ams" are AMS specific commands. These commands are defined in the "amsSetup.tcl" file which is a TCL script created by the "ams_edis" script. This "amsSetup.tcl" script invokes Cadence commands; later you will write your own TCL script to invoke the commands needed to place and route your design.

Specify Floor Plan

At the floor planning stage we divide the chip into different areas some of which may be used for standard cells while others will be used for macro blocks such as ROMs and RAMs. In this simple design a single area for all of the standard cells should be enough.

• The "floorPlan" instruction below specifies a core aspect ratio of 1 (i.e. 1:1 or square) and row density of 0.7 (i.e. 70% utilisation). The command will also leave a space of 60µm between the core area and the pad ring which will be used for the core power rings.

      floorPlan -r 1 0.7 60 60 60 60
  

Add Core Power Rings

• Specify the connectivity of the global power nets

      amsGlobalConnect both
  

• Add the gnd! and vdd! power rings in the centre of the space around the core using metal 3 and metal 4 with a width of 20µm and a spacing of 2µm

      addRing \
        -type core_rings \
        -nets {gnd! vdd!} \
        -center 1 \
        -layer {bottom MET3 top MET3 right MET4 left MET4} \
        -width 20 -spacing 2
  

Add Power Routing

Once the power rings have been added we can perform the power routing for the connections to the pad cells and the core rows which will later hold the standard cells.

• Add routing for vdd! and gnd! (special route)

      sroute \
        -connect { blockPin padPin padRing corePin floatingStripe } \
        -layerChangeRange { MET1 MET4 } \
        -blockPinTarget { nearestTarget } \
        -padPinPortConnect { allPort oneGeom } \
        -padPinTarget { nearestTarget } \
        -corePinTarget { firstAfterRowEnd } \
        -floatingStripeTarget { blockring padring ring stripe ringpin blockpin followpin } \
        -allowJogging 1 \
        -crossoverViaLayerRange { MET1 MET4 } \
        -nets { vdd! gnd! } \
        -allowLayerChange 1 \
        -blockPin useLef \
        -targetViaLayerRange { MET1 MET4 }
  

• At this stage you should save your work.

      saveDesign floorplan.enc
  

  The "floorplan.enc" file specified in the command does not contain the design data itself but it does contain information required to restore the saved design later (the design data itself is stored in a Cadence library directory named "FEOADesignlib" with a cell name "<topcell>" and a view name "floorplan").

  If you need to recover this version of the design later, you can start encounter with the following options: encounter -init floorplan.enc -win

Place cells

The next stage is to place the standard cells in the core.

• Change from flooplan view to placement view so that we can see the cells

      setDrawView place
  

• Place standard cells in rows and cap cells at the end of each row.

      placeDesign
      amsAddEndCaps
  

• Add Tiehi/Tielo cells

      setTieHiLoMode -cell {LOGIC1 LOGIC0} -maxFanout 10
      addTieHiLo
  

  This will replace any '1' or '0' signals in the Verilog netlist with safer connections to the TieHi and TieLo cells.

• Save intermediate design

      saveDesign placed.enc
  

Note that the "placeDesign" command seems to have added wiring as well as cells. The wiring that you see is as a result of a trial routing stage and will later be replaced by the actual routing.

Pre-CTS Optimisation

During optimisation the tool can add buffers to reduce delays in high capacitance paths. Other optimisations that can take place at this stage include the re-sizing of gates (to increase drive strength or to decrease capacitive load) and the movement of gates to reduce path lengths.

• Run the optimisation command in "Pre-CTS" mode

      optDesign -preCTS
  

  This is the first of three optimisation stages, identified as "Pre-CTS" because it happens before Clock Tree Synthesis.

If all is well, you will see a section marked "optDesign Final Summary" which shows no "Setup mode" "Violating Paths" and no nets with design rule violations (DRVs).

If there are oustanding problems at this stage, seek advice. It may be worthwhile running a further optimisation at this stage in order to improve the design before proceding.

Clock Tree Synthesis

• In the commands below, we specify the operation mode for the clock tree synthesis and create a clock tree specification file in the CONSTRAINTS directory:

      setCTSMode -engine ck
  
      setCTSMode -traceDPinAsLeaf true -traceIOPinAsLeaf true
  
      createClockTreeSpec \
        -bufferList {CLKBU2 CLKBU4 CLKBU6 CLKBU8 CLKBU12 CLKBU15 CLKIN0 CLKIN1 CLKIN2 CLKIN3 CLKIN4 CLKIN6 CLKIN8 CLKIN10 CLKIN12 CLKIN15} \
        -routeClkNet -output CONSTRAINTS/clock.clk
  
  

• Here we use the clock tree specification file to specify the clock tree and then run the synthesis

      specifyClockTree -file CONSTRAINTS/clock.clk
  
      ckSynthesis
  

• Save intermediate design

      saveDesign inc_clock_tree.enc
  

Update Constraints

The original constraints file included instructions to set the clock latency, clock transition and clock uncertainty in order to model the predicted delay through the clock tree and the jitter in the input clock. Now that we have a real clock tree we need to update the constraints to reflect the delays through this tree.

• The first instruction says that we will be modifying both the functional mode and the test mode constraints:

      set_interactive_constraint_modes {func test}
  

• Replace predicted latency and transition with actual values through clock tree:

      set_propagated_clock [all_clocks]
  

• Previously the clock uncertainty was set to 1 ns to reflect a combination of the effect of the clock skew and the jitter in the input clock. Now we will reduce the uncertainty to 0.5 ns to reflect only the jitter in the input clock since the clock skew can be calculated from the differences in delay through the clock tree:

      set_clock_uncertainty -setup 0.5 [get_clocks master_clock]
      set_clock_uncertainty -hold 0.1 [get_clocks master_clock]
  

  This time we split the uncertainty for the setup and hold tests since jitter affects setup calculations but not hold calculations. Having a non-zero value for the clock uncertainty related to hold increases our confidence that the design will work if the skew in the clock tree is miscalculated.

Post-CTS Optimisation

Based on the design including the clock tree and the updated constraints a new round of optimisations is run. At this stage we are interested in particular in hold vioalations caused by problems with clock skew.

• Set the parameters and then run the optimisation:

      set_analysis_view -setup {func_max func_typ func_min} -hold {func_max func_typ func_min}
  

      optDesign -postCTS -hold
  

As before you should check the "optDesign Final Summary" from each of the "optDesign" commands to check for problems.

Route Design

Although various trial routing has already taken place during the optimisation and clock tree synthesis stages, onlt the power routing that we did at the beginning of the process is fixed. Now that all the cells are in place, we are ready to route the design for real.

• Signal routing (nanoRoute)

      routeDesign -globalDetail
  

Post-Route Optimisation

At this stage the design is nominally complete but may have errors. The final optimisation stage aims to identify and resolve any remaining problems.

• Set the parameters and then run the optimisations:

      setDelayCalMode -engine default -siAware true
      setAnalysisMode -analysisType onChipVariation
  
      optDesign -postRoute -hold
      optDesign -postRoute
      optDesign -postRoute -drv
  

Add Core Filler Cells

Filler cells are needed for the core to join the wells and to add well and substrate taps.

• Add AMS specified core filler cells:

      amsFillcore
  

Verify the Design

While the tools will do their best to generate a design rule correct layout which matches the connectivity of the original design, things do go wrong. At this stage you should run the following verify commands and check for any violations.

• Verify Connectivity:

      verifyConnectivity
  

• Verify Geometry:

      verifyGeometry
  

Check the Size of the Design

• The size of the design is important since it determines the fabrication cost. While you can find the extent of the design using the GUI, there is a command line method for accurate measurement:

      dbGet top.fPlan.boxes
  

  (the numbers returned are the x and y co-ordinates of the lower left corner of the chip followed by the x and y co-ordinates of the upper right corner)

Save the Design

• Save final design in a form to be loaded back in to encounter:

      saveDesign routed.enc
  

• Save the design in various formats including as a GDS II file <topcell>_final_fe.gds which is the file used for fabrication and a Verilog netlist file <topcell>_final.v which will be used for post-layout simulations:

      amsWrite final
  

• Save an SDF file SDF/<topcell>_func_max.sdf for post-layout simulation based on worst case delays:

      amsWriteSDF4View {func_max}
  

Scripting the design flow

The whole procedure can be automated using a tcl script. This is especially useful if having created a chip layout, you make a minor change to the design and need to go through the whole process again.

Within encounter, the script can be executed using the command: source <scriptname>.tcl

• Example script:

  
  # set the io file name and boolean for scan path (these lines will need to be customised)
  
      set io_filename ../padring/<topcell>.io
      set scan_path_included <true|false>
  
  # load custom script
  
      source edi_custom_c35b4.tcl
  
  # initialise the database (load in the design)
  
      amsDbSetup
  
  # if your design supports one, specify a scan chain
  
      if { $scan_path_included } { specifyScanChain ScanChain0 -start SDI -stop SDO }
  
  # timing setup
  
      amsSetMMMC
      amsSetAnalysisView minmax {func test}
  
  # Place the pad cells (including corners and power)
  
      loadIoFile $io_filename
  
  # view design in gui
  
      fit
  
  # create some space for the power rings
  # 60um spacing is plenty for 2x 20 um power rings
  
      floorPlan -r 1 0.7 60 60 60 60
  
  # Snap the pad cells to the 0.1 um grid with spacing divisible by 1 um
  
      snap_ams_pads
  
  # Add peripheral filler cells
  
      amsFillperi
  
  # specify the connectivity of for the power nets
  
      amsGlobalConnect both
  
      globalNetConnect gnd! -type pgpin -pin A -inst CORE_GND_* -module {}
      globalNetConnect vdd! -type pgpin -pin A -inst CORE_VDD_* -module {}
  
  # add the power rings (note a 20um ring is classed as "wide metal" - >10um)
  # spacing of 2um is minimum for thick MET4
  
      addRing \
        -type core_rings \
        -nets {gnd! vdd!} \
        -center 1 \
        -layer {bottom MET3 top MET3 right MET4 left MET4} \
        -width 20 -spacing 2
  
  # add power and ground routing (special route)
  
      sroute \
        -connect { blockPin padPin padRing corePin floatingStripe } \
        -layerChangeRange { MET1 MET4 } \
        -blockPinTarget { nearestTarget } \
        -padPinPortConnect { allPort oneGeom } \
        -padPinTarget { nearestTarget } \
        -corePinTarget { firstAfterRowEnd } \
        -floatingStripeTarget { blockring padring ring stripe ringpin blockpin followpin } \
        -allowJogging 1 \
        -crossoverViaLayerRange { MET1 MET4 } \
        -nets { vdd! gnd! } \
        -allowLayerChange 1 \
        -blockPin useLef \
        -targetViaLayerRange { MET1 MET4 }
  
  # Save intermediate design
  
      saveDesign floorplan.enc
  
  # -------------------
  # to start again here type:   encounter -init floorplan.enc -win
  # -------------------
  
  # Placement
  
      setDrawView place
  
      placeDesign
      amsAddEndCaps
  
  # Add Tiehi/Tielo cells
  
      setTieHiLoMode -cell {LOGIC1 LOGIC0} -maxFanout 10
      addTieHiLo
  
  # Save intermediate design
  
      saveDesign placed.enc
  
  # -------------------
  # to start again here type:   encounter -init placed.enc -win
  # -------------------
  
  # Pre-CTS Optimisation
  
      optDesign -preCTS
  
  # Clock Tree Synthesis
  
      setCTSMode -engine ck
  
      setCTSMode -traceDPinAsLeaf true -traceIOPinAsLeaf true
  
      createClockTreeSpec \
        -bufferList {CLKBU2 CLKBU4 CLKBU6 CLKBU8 CLKBU12 CLKBU15 CLKIN0 CLKIN1 CLKIN2 CLKIN3 CLKIN4 CLKIN6 CLKIN8 CLKIN10 CLKIN12 CLKIN15} \
        -routeClkNet -output CONSTRAINTS/clock.clk
  
      specifyClockTree -file CONSTRAINTS/clock.clk
  
      ckSynthesis
  
  # Save intermediate design
  
      saveDesign inc_clock_tree.enc
  
  # -------------------
  # to start again here type:   encounter -init inc_clock_tree.enc -win
  # -------------------
  
  # Post-CTS - update constraints
  
      set_interactive_constraint_modes {func test}
  
  # replace predicted latency and transition with actual values through clock tree
  
      set_propagated_clock [all_clocks]
  
  # set jitter to 0.5 ns (clock skew is no longer important)
  
      set_clock_uncertainty -setup 0.5 [get_clocks master_clock]
      set_clock_uncertainty -hold 0.1 [get_clocks master_clock]
  
  # Post-CTS Optimisation
  
      set_analysis_view -setup {func_max func_typ func_min} -hold {func_max func_typ func_min}
  
      optDesign -postCTS -hold
  
  # route with nanoRoute
  
      routeDesign -globalDetail
  
  # Post-route optimisation
  
      setDelayCalMode -engine default -siAware true
      setAnalysisMode -analysisType onChipVariation
  
      optDesign -postRoute -hold
      optDesign -postRoute
      optDesign -postRoute -drv
  
  # Add core filler cells after optimisation as suggested by Michael Nydegger (but not by RAL)
  
      amsFillcore
  
  # Verify connectivity and geometry
  
      verifyConnectivity
      verifyGeometry
  
  # Get size of design
  
      set size [ dbGet top.fPlan.boxes ]
      print "CHIP SIZE IS $size"
  
  # Save final design
  
      saveDesign routed.enc
      amsWrite final
      amsWriteSDF4View {func_max}
  
  # -------------------
  # to start again here type:   encounter -init routed.enc -win
  # -------------------
  
  

While this first script does everything that we need, it doesn't care about the results of an individual operation and will carry on regardless of failures such as unresolved timing violations during the optimisation stages.

A more advanced script will use the timeDesign and get_metric commands to halt operations if a problem is identified.

• Advanced script:

  
  # set the io file name and boolean for scan path (these lines will need to be customised)
  
      set io_filename ../padring/<topcell>.io
      set scan_path_included <true|false>
  
  # load custom script
  
      source edi_custom_c35b4.tcl
  
  # initialise the database (load in the design)
  
      amsDbSetup
  
  # if your design supports one, specify a scan chain
  
      if { $scan_path_included } { specifyScanChain ScanChain0 -start SDI -stop SDO }
  
  # timing setup
  
      amsSetMMMC
      amsSetAnalysisView minmax {func test}
  
  # Place the pad cells (including corners and power)
  
      if { ! [file exists $io_filename] } {
        print "NO I/O FILE: $io_filename - GIVING UP"
        return
      }
  
      loadIoFile $io_filename
  
  # view design in gui
  
      fit
  
  # create some space for the power rings
  # 60um spacing is plenty for 2x 20 um power rings
  
      floorPlan -r 1 0.7 60 60 60 60
  
  # Snap the pad cells to the 0.1 um grid with spacing divisible by 1 um
  
      snap_ams_pads
  
  # Add peripheral filler cells
  
      amsFillperi
  
  # specify the connectivity of for the power nets
  
      amsGlobalConnect both
  
      globalNetConnect gnd! -type pgpin -pin A -inst CORE_GND_* -module {}
      globalNetConnect vdd! -type pgpin -pin A -inst CORE_VDD_* -module {}
  
  # add the power rings (note a 20um ring is classed as "wide metal" - >10um)
  # spacing of 2um is minimum for thick MET4
  
      addRing \
        -type core_rings \
        -nets {gnd! vdd!} \
        -center 1 \
        -layer {bottom MET3 top MET3 right MET4 left MET4} \
        -width 20 -spacing 2
  
  # add power and ground routing (special route)
  
      sroute \
        -connect { blockPin padPin padRing corePin floatingStripe } \
        -layerChangeRange { MET1 MET4 } \
        -blockPinTarget { nearestTarget } \
        -padPinPortConnect { allPort oneGeom } \
        -padPinTarget { nearestTarget } \
        -corePinTarget { firstAfterRowEnd } \
        -floatingStripeTarget { blockring padring ring stripe ringpin blockpin followpin } \
        -allowJogging 1 \
        -crossoverViaLayerRange { MET1 MET4 } \
        -nets { vdd! gnd! } \
        -allowLayerChange 1 \
        -blockPin useLef \
        -targetViaLayerRange { MET1 MET4 }
  
  # Check to see if there are problems with the floorplan (e.g. gaps between pad cells)
  
      verifyGeometry
  
      if { [get_metric -value verify.geom.total] != 0 } {
        print "FLOORPLAN GEOMETRY CHECK FAILED - GIVING UP"
        return
      }
  
  # Save intermediate design
  
      saveDesign floorplan.enc
  
  # -------------------
  # to start again here type:   encounter -init floorplan.enc -win
  # -------------------
  
  # Placement
  
      setDrawView place
  
      placeDesign
      amsAddEndCaps
  
  # Add Tiehi/Tielo cells
  
      setTieHiLoMode -cell {LOGIC1 LOGIC0} -maxFanout 10
      addTieHiLo
  
  # Save intermediate design
  
      saveDesign placed.enc
  
  # -------------------
  # to start again here type:   encounter -init placed.enc -win
  # -------------------
  
  # Pre-CTS Optimisation
  
      optDesign -preCTS
  
  # Check Timing
  
     timeDesign -preCTS
  
     if { [get_metric -value timing.setup.numViolatingPaths.all] != 0 } {
       print "PRECTS SETUP CHECK FAILED - GIVING UP"
       return
     }
  
  
  # Clock Tree Synthesis
  
      setCTSMode -engine ck
  
      setCTSMode -traceDPinAsLeaf true -traceIOPinAsLeaf true
  
      createClockTreeSpec \
        -bufferList {CLKBU2 CLKBU4 CLKBU6 CLKBU8 CLKBU12 CLKBU15 CLKIN0 CLKIN1 CLKIN2 CLKIN3 CLKIN4 CLKIN6 CLKIN8 CLKIN10 CLKIN12 CLKIN15} \
        -routeClkNet -output CONSTRAINTS/clock.clk
  
      specifyClockTree -file CONSTRAINTS/clock.clk
  
      ckSynthesis
  
  # Save intermediate design
  
      saveDesign inc_clock_tree.enc
  
  # -------------------
  # to start again here type:   encounter -init inc_clock_tree.enc -win
  # -------------------
  
  # Post-CTS - update constraints
  
      set_interactive_constraint_modes {func test}
  
  # replace predicted latency and transition with actual values through clock tree
  
      set_propagated_clock [all_clocks]
  
  # set jitter to 0.5 ns (clock skew is no longer important)
  
      set_clock_uncertainty -setup 0.5 [get_clocks master_clock]
      set_clock_uncertainty -hold 0.1 [get_clocks master_clock]
  
  # Post-CTS Optimisation
  
      set_analysis_view -setup {func_max func_typ func_min} -hold {func_max func_typ func_min}
  
      optDesign -postCTS -hold
  
  # Check Timing
  
     timeDesign -postCTS -hold
  
     if { [get_metric -value timing.setup.numViolatingPaths.all] != 0 } {
       print "POSTCTS SETUP CHECK FAILED - GIVING UP"
       return
     }
  
     if { [get_metric -value timing.hold.numViolatingPaths.all] != 0 } {
       print "POSTCTS HOLD CHECK FAILED - GIVING UP"
       return
     }
  
  
  # route with nanoRoute
  
      routeDesign -globalDetail
  
  # Post-route optimisation
  
      setDelayCalMode -engine default -siAware true
      setAnalysisMode -analysisType onChipVariation
  
      optDesign -postRoute -hold
      optDesign -postRoute
      optDesign -postRoute -drv
  
  # Check Timing
  
     timeDesign -postRoute -hold
  
     if { [get_metric -value timing.setup.numViolatingPaths.all] != 0 } {
       print "POSTROUTE SETUP CHECK FAILED - GIVING UP"
       return
     }
  
     if { [get_metric -value timing.hold.numViolatingPaths.all] != 0 } {
       print "POSTROUTE HOLD CHECK FAILED - GIVING UP"
       return
     }
  
  
  # Add core filler cells after optimisation as suggested by Michael Nydegger (but not by RAL)
  
      amsFillcore
  
  # Verify connectivity and geometry
  
      verifyConnectivity
  
      if { [get_metric -value verify.conn] != 0 } {
        print "CONNECTIVITY CHECK FAILED - GIVING UP"
        return
      }
  
      verifyGeometry
  
      if { [get_metric -value verify.geom.total] != 0 } {
        print "GEOMETRY CHECK FAILED - GIVING UP"
        return
      }
  
  # Get size of design
  
      set size [ dbGet top.fPlan.boxes ]
      print "CHIP SIZE IS $size"
  
  # Save final design
  
      saveDesign routed.enc
      amsWrite final
      amsWriteSDF4View {func_max}
  
  # -------------------
  # to start again here type:   encounter -init routed.enc -win
  # -------------------
  
      print "PLACE AND ROUTE COMPLETED"