#
# set constraints for a 50 MHz clock (Period = 20ns)
#


create_clock -period 20 -name master_clock [get_ports Clock]

#
# clock constraints
#
# * the latency value here models the predicted delay through the clock tree
#   - this value is discarded after clock tree synthesis by the 'set_propagated_clock' instruction
#
# * variation in the clock transition value has a significant effect on clock tree generation
#   - AMS recommends setting the clock transition to 2.0 ns to reduce the number of inserted clock buffers/inverters
#   - (in this demo, a smaller value has been used to ensure that at least some clock tree components are inserted)
#
# * the uncertainty value here models the combined effect of clock jitter and predicted clock skew
#   - folowing clock tree insertion, this value must be reduced so that only clock jitter is modelled
#

set_clock_latency     2.5 [get_clocks master_clock]
set_clock_transition  0.5 [get_clocks master_clock]
set_clock_uncertainty 1.0 [get_clocks master_clock]

#
# configure output constraints
#

set_output_delay 8.0 -max -network_latency_included -clock master_clock [all_outputs]
set_output_delay 0.5 -min -network_latency_included -clock master_clock [all_outputs]

set_load 1.0  -max [all_outputs]
set_load 0.01 -min [all_outputs]

#
# configure input constraints
#
# ( remove_from_collection is tcl not sdc so we must source this file rather than read_sdc into DC )
#

set_input_delay 12.0 -max -network_latency_included -clock master_clock [remove_from_collection [all_inputs] [get_ports Clock]]
set_input_delay 0.5 -min -network_latency_included -clock master_clock [remove_from_collection [all_inputs] [get_ports Clock]]

# - set_driving_cell command for DC: set_driving_cell -max -library c35_IOLIB_WC -lib_cell BU24P -pin PAD [all_inputs]
# - set_driving_cell command for DC: set_driving_cell -min -library c35_IOLIB_WC -lib_cell BU1P -pin PAD [all_inputs]
# for Encounter with MMMC we should let the tool get the BU24P/BU1P cell from any library in the available "library set":

set_driving_cell -max -lib_cell BU24P -pin PAD [all_inputs]
set_driving_cell -min -lib_cell BU1P -pin PAD [all_inputs]

#
# don't worry about nReset timing
#

set_false_path -from [get_ports nReset]

#
# optimise for area (after timing)
#

set_max_area 0