SPARCjnr - Simulation of a Pipelined Processor

A SPARC like pipelined processor has been designed using Verilog Hardware Description Language. The design uses a 5 stage pipeline and a Harvard memory architecture. A subset of the full SPARC instruction set is supported. The subset is that described within your course notes and in the SPARCjnr - Introduction and Instruction Set documentation.

For this exercise you must investigate the behaviour of the design using the Verilog XL simulator. This advanced digital simulator allows you to track bus and register values as the simulated machine executes a machine code program.

Exercise Format

No formal lab time is set aside for this exercise and no marks will be awarded for completion. Completion of this exercise is therefore solely to help you to understand the detailed operation of a pipelined processor (this should help with your exam).

The exercise should take about 4 hours to complete.

The simulation will only run on a Sun computer, in particular the Sun computers in the Shackleton computer room (Building 44 room 1061).

Exercise 1

Initialise your environment by typing the following command in a terminal or xterm window:
```
	/home/bim/script/aca/init_sparc_jnr
```
this command will
- create a working directory ~/design/verilog/ups/sparc_jnr
- copy the files sparc_sim, ex1.v, ex2.asm and ex3.asm to that directory
- open a new xterm window set to the correct directory
  (you will use this new xterm for the rest of the lab)
The following assembly language instructions are coded in the file ex1.v:
```
	ADD  R0,1,  R1
	ADD  R0,2,  R2
	ADD  R0,3,  R3
	ADD  R0,4,  R4
	XOR  R2,7,  R5
	SLL  R3,R1, R6
```
Open an editing window in order to examine this file.

Using your notes as reference, confirm (or otherwise) that the machine code instructions match the assembly language comments.

Explain each instruction and hence derive the final register values.

Calculate the number of cycles required to execute these instructions using the five stage pipeline processor.
Use the simulator to investigate the execution of this code.
```
	verilog_gui -f sparc_sim ex1.v
```
Follow each instruction through each stage of the pipe.

Are the outcome and the time taken as predicted?

Exercise 2

The file ex2.asm is an assembly laguage version of the program defined in ex1.v.

Run the simulator again with no program file specified:
```
	verilog_gui -f sparc_sim
```
and load in the assembly language file ex2.asm from the file menu.

Confirm that the operation is the same as before.
Append the following instructions to the program file ex2.asm and reload the file into the simulator.
```
	ADD  R5,R2, R7
	SLL  R7,R4, R8
	XNOR R7,R8, R9
```
Show that feed forward is required by each of these instructions. Sketch a diagram for each instruction illustrating the feed forward paths used.
The following instruction is a pseudo-instruction. Since it is not possible to store a 32 bit immediate value within a single instruction, it must be coded as two separate instructions. You should code this as a SETHI instruction combined with another instruction of your choice and append it to your program.
```
	SET 0xABCD1234, R10
```
Append the following instructions to the program.
```
	ST   R10,   (R5+R3)
	LD  (R0+8),  R11
```
As before, investigate any feed forward required.

Append the following instructions to the program.

	SUB  R0,R11,  R12
	XNOR R10,R7,  R13
	XOR  R12,R13, R14

Explain why this code demonstrates a hazard.
Draw a diagram illustrating the progression of the last five instructions through the pipeline. What action is taken by the processor in order to avoid an incorrect result.
Re-arrange the instructions in order to avoid the hazard.

Exercise 3

The assembly language file ex3.asm contains the following instructions:

	ADD   R0,8,  R1
	ADD   R1,R0, R2
.loop	ADD   R1,1,  R1
	SLL   R2,4,  R2
	ADD   R2,R1, R2
	SUBcc R1,15, R0
	BNE   .loop
	NOP
	XNOR  R0,R2, R2

Run this code as you did for ex2.asm.
Write down the sequence of values for R1 and R2. Is this the sequence you would expect?
Explain the function of the NOP instruction.
How many cycles does the program take to complete?

Exercise 3a

Re-write the program to use BNE,a instead of BNE such that the delay slot may be put to good use. Save the new file as "ex3a.asm".
How many cycles does the new program take to complete?

Exercise 3b

Instead of using BNE,a re-order the program instructions to make more efficient use of the delay slot. Save the new file as "ex3b.asm".
How many cycles does this version take to complete?

Exercise 3c

Re-write the program such that the following part of the code is done in a subroutine invoked by CALL.
```
	ADD   R1,1,  R1
	SUBcc R1,15, R0
```
Save the new file as "ex3c.asm".

Iain McNally

12-2-2002