Build a parallel computer (using ARM cores)
A number of past projects have been undertaken in this area looking at the different types of multi-core parallel computers that may be built as a system-on-chip to be implemented on an FPGA.
Programming skills are useful here since an important part of the work involves writing code to test the designed processor.
This project will involve the passing of messages between two or more clusters of processors each of which employs a shared-memory architecture. Message passing should be controlled by a DMA (direct memory access) engine which competes with the cluster processors for access to the shared memory.
This architecture should be suitable for extension to a multi-FPGA solution if time permits, with a single shared-memory cluster on each FPGA and inter-FPGA communications using message passing.
Build a parallel computer (using ARM cores)
A number of past projects have been undertaken in this area looking at the different types of multi-core parallel computers that may be built as a system-on-chip to be implemented on an FPGA.
Programming skills are useful here since an important part of the work involves writing code to test the designed processor.
This project will include two or more FPGAs with the network split between them. The FPGAs will not share the same clock so the communication between FPGAs will need to be asynchronous. I particular, this year's project will look at the problem of multiple virtual channels between FPGAs.
Build an FPGA System on Chip capable of running a video game and then create a game to run on the system.
A number of past projects have been undertaken in this area, each with a different emphasis. Most of these projects include the design of specialist video and/or audio peripherals for the system which allow games to be designed with the limited resources available on a small system on chip.
For this project the aim will be to include communication between two FPGA SoC systems to allow two players to compete (with each seeing a different view of the game on their local display).
Build an FPGA System on Chip capable of running a video game and then create a game to run on the system.
A number of past projects have been undertaken in this area, each with a different emphasis. Most of these projects include the design of specialist video and/or audio peripherals for the system which allow games to be designed with the limited resources available on a small system on chip.
For this project, the aim will be to produce graphics hardware capable of exploiting data parallelism and pipeline techniques to accelerate the rendering of triangles.
A number of students have looked into the problem of place and route for standard cells created using the Magic VLSI editor. The designs created so far have been standalone tools which interact with Magic via its simple and well-defined text-based file formats.
Magic already includes a little-used module for automated routing. The existing routing algorithm is designed for routing around cells (e.g. routing in channels) rather than routing over cells. The aim of this project is to integrate an alternative over-cell routing algorithm into the existing Magic code.
This project is suitable for a student who is taking ELEC3221 VLSI Systems Design in semester 1.
Previous experience of programming in 'C' is essential for this project in order to understand and build on the existing code base.
A number of students have looked into the problem of generating SRAM macrocells for use in IC design. This project will take that work a stage further by investigating the requirements for integration of these macrocells into our standard Synopsys and Cadence design flow.
The overall aim will be to produce a program that is able to generate a custom SRAM along with all of its models and to demonstrate its functionality by including a generated SRAM in a fully verified system-on-chip design.
This project is suitable for a student who is taking ELEC6230 VLSI Systems Design in semester 1.
Programming skills are useful here since an important part of the work involves writing code to generate macrocells from simple building blocks.
Iain McNally
30-11-2020