| Task |
Percentage Effort on each Task |
|||||
|---|---|---|---|---|---|---|
| ECSID: |
_________ |
_________ |
_________ |
_________ |
_________ |
|
| 1 |
rdtype |
|||||
| 2 |
smux2 |
|||||
| 3 |
smux3 |
|||||
| 4 |
mux2 |
|||||
| 5 |
fulladder |
|||||
| 6 |
halfadder |
|||||
| 7 |
xor2 |
|||||
| 8 |
inv |
|||||
| 9 |
nand2 |
|||||
| 10 |
nand3 |
|||||
| 11 |
nand4 |
|||||
| 12 |
nor2 |
|||||
| 13 |
nor3 |
|||||
| 14 |
and2 |
|||||
| 15 |
or2 |
|||||
| 16 |
trisbuf |
|||||
| 17 |
buffer |
|||||
| 18 |
leftbuf |
|||||
| 19 |
rightend |
|||||
| 20 |
tiehigh |
|||||
| 21 |
tielow |
|||||
| 22 |
rowcrosser |
|||||
| 23 |
scandtype |
|||||
| 24 |
scanreg |
|||||
| 25 |
Verilog Simulation |
|||||
| 26 |
Calibre Design Rule Checking |
|||||
| 26 |
HSpice Characterization |
|||||
| 27 |
Script for Cell Library Databook (leave blank if databook is manually generated) |
|||||
| 28 |
Manual Generation of Cell Library Databook (leave blank if databook created by script) |
|||||
| 29 |
Design Exercise Report (words) |
|||||
| 30 |
Design Exercise Report (figures) |
|||||
| OVERALL EFFORT |
||||||
| Signature: |
||||||