Netlist File # Please note that the magic router is very fussy about the format of this # file. Spaces are important; any line beginning with a space is ignored; # if a space is included at the end of a terminal name the routing will fail. # Type "man -s 5 net" for further details. # multiplier.net # # # This file assumes two sub-modules: control (instance name control_0) and # datapath (instance name datapath_0) # It also assumes bus signals (Operand1, Operand2, Result) use square brackets # for index values # The control and feedback signals listed are those for a Type#1 multiplier # # If your design does not match these assumptions then you will have to edit # this file # The required labels within datapath are: # Vdd! # GND! # Clock # nReset # Test # SDI # SDO # Operand1[0] # Operand1[1] # Operand1[2] # Operand1[3] # Operand1[4] # Operand1[5] # Operand1[6] # Operand1[7] # Operand2[0] # Operand2[1] # Operand2[2] # Operand2[3] # Operand2[4] # Operand2[5] # Operand2[6] # Operand2[7] # Result[0] # Result[1] # Result[2] # Result[3] # Result[4] # Result[5] # Result[6] # Result[7] # Add # Decrement # EnableOp1 # EnableOp2 # EnableZero # EnableA # EnableACC # LoadA # LoadB # LoadACC # LoadR # Underflow # The required labels within control unit are: # Vdd! # GND! # Clock # nReset # Test # SDI # SDO # Req # Done # Add # Decrement # EnableOp1 # EnableOp2 # EnableZero # EnableA # EnableACC # LoadA # LoadB # LoadACC # LoadR # Underflow # # Core power and ground pads: # (These should be wired first by hand to ensure that wide enough metal tracks # are used) # # For input pads: # OEN signals are pulled high to disable output behaviour # IE signals are pulled high to enable input behaviour # I signals are pulled high to stop them from floating # # For output pads: # OEN signals are pulled low to enable output behaviour # IE signals are pulled low to disable input behaviour # # For all pads: # PE signals are pulled low to disable pull-down behaviour # DS signals are pulled low to contol slew rate # datapath_0/Vdd! control_0/Vdd! VDDcore/Vdd! Clock/OEN nReset/OEN Test/OEN SDI/OEN Req/OEN Operand1_0/OEN Operand1_1/OEN Operand1_2/OEN Operand1_3/OEN Operand1_4/OEN Operand1_5/OEN Operand1_6/OEN Operand1_7/OEN Operand2_0/OEN Operand2_1/OEN Operand2_2/OEN Operand2_3/OEN Operand2_4/OEN Operand2_5/OEN Operand2_6/OEN Operand2_7/OEN Clock/IE nReset/IE Test/IE SDI/IE Req/IE Operand1_0/IE Operand1_1/IE Operand1_2/IE Operand1_3/IE Operand1_4/IE Operand1_5/IE Operand1_6/IE Operand1_7/IE Operand2_0/IE Operand2_1/IE Operand2_2/IE Operand2_3/IE Operand2_4/IE Operand2_5/IE Operand2_6/IE Operand2_7/IE Clock/I nReset/I Test/I SDI/I Req/I Operand1_0/I Operand1_1/I Operand1_2/I Operand1_3/I Operand1_4/I Operand1_5/I Operand1_6/I Operand1_7/I Operand2_0/I Operand2_1/I Operand2_2/I Operand2_3/I Operand2_4/I Operand2_5/I Operand2_6/I Operand2_7/I datapath_0/GND! control_0/GND! VSScore/GND! SDO/OEN Done/OEN Result_0/OEN Result_1/OEN Result_2/OEN Result_3/OEN Result_4/OEN Result_5/OEN Result_6/OEN Result_7/OEN SDO/IE Done/IE Result_0/IE Result_1/IE Result_2/IE Result_3/IE Result_4/IE Result_5/IE Result_6/IE Result_7/IE SDO/PE Done/PE Result_0/PE Result_1/PE Result_2/PE Result_3/PE Result_4/PE Result_5/PE Result_6/PE Result_7/PE Clock/PE nReset/PE Test/PE SDI/PE Req/PE Operand1_0/PE Operand1_1/PE Operand1_2/PE Operand1_3/PE Operand1_4/PE Operand1_5/PE Operand1_6/PE Operand1_7/PE Operand2_0/PE Operand2_1/PE Operand2_2/PE Operand2_3/PE Operand2_4/PE Operand2_5/PE Operand2_6/PE Operand2_7/PE SDO/DS Done/DS Result_0/DS Result_1/DS Result_2/DS Result_3/DS Result_4/DS Result_5/DS Result_6/DS Result_7/DS Clock/DS nReset/DS Test/DS SDI/DS Req/DS Operand1_0/DS Operand1_1/DS Operand1_2/DS Operand1_3/DS Operand1_4/DS Operand1_5/DS Operand1_6/DS Operand1_7/DS Operand2_0/DS Operand2_1/DS Operand2_2/DS Operand2_3/DS Operand2_4/DS Operand2_5/DS Operand2_6/DS Operand2_7/DS # # Input pads: # datapath_0/Clock control_0/Clock Clock/C datapath_0/nReset control_0/nReset nReset/C datapath_0/Test control_0/Test Test/C datapath_0/SDI SDI/C control_0/Req Req/C datapath_0/Operand1[0] Operand1_0/C datapath_0/Operand1[1] Operand1_1/C datapath_0/Operand1[2] Operand1_2/C datapath_0/Operand1[3] Operand1_3/C datapath_0/Operand1[4] Operand1_4/C datapath_0/Operand1[5] Operand1_5/C datapath_0/Operand1[6] Operand1_6/C datapath_0/Operand1[7] Operand1_7/C datapath_0/Operand2[0] Operand2_0/C datapath_0/Operand2[1] Operand2_1/C datapath_0/Operand2[2] Operand2_2/C datapath_0/Operand2[3] Operand2_3/C datapath_0/Operand2[4] Operand2_4/C datapath_0/Operand2[5] Operand2_5/C datapath_0/Operand2[6] Operand2_6/C datapath_0/Operand2[7] Operand2_7/C # # Output pads: # control_0/SDO SDO/I control_0/Done Done/I datapath_0/Result[0] Result_0/I datapath_0/Result[1] Result_1/I datapath_0/Result[2] Result_2/I datapath_0/Result[3] Result_3/I datapath_0/Result[4] Result_4/I datapath_0/Result[5] Result_5/I datapath_0/Result[6] Result_6/I datapath_0/Result[7] Result_7/I # # Internal Scan Path: # datapath_0/SDO control_0/SDI # # Control Signals: # control_0/Add datapath_0/Add control_0/Decrement datapath_0/Decrement control_0/EnableOp1 datapath_0/EnableOp1 control_0/EnableOp2 datapath_0/EnableOp2 control_0/EnableZero datapath_0/EnableZero control_0/EnableA datapath_0/EnableA control_0/EnableACC datapath_0/EnableACC control_0/LoadA datapath_0/LoadA control_0/LoadB datapath_0/LoadB control_0/LoadACC datapath_0/LoadACC control_0/LoadR datapath_0/LoadR # # Feedback Signals: # control_0/Underflow datapath_0/Underflow # # End of netlist