Introduction
The purpose of this laboratory is to investigate a real RISC processor and hence to improve your understanding of RISC processor operation.
The processor chosen is the LSI L64801 SPARC. The diagram below shows a best guess at the internal architecture of this processor:
The major features that distinguish this processor from the simplified processors described in the lecture notes are:
Equipment
You will be working with the RISC Experimenter Board (REB) which is a single-card SPARC-based microcomputer system (or Single Card Computer (SCC)). The circuit board is not enclosed so all the components and wiring can be clearly seen. The circuit board is double-sided with components mounted on one side only. This forces the components on the board to be less densely packed than a commercial SCC. A top view of the REB is shown in the appendix.
Because the REB is open please be careful when using probes and wires. Careless use will cause (expensive) damage and considerable inconvenience to you and others. Only use the provided REB power supply. Do not make alterations to the circuit, such as adding an extension card or making prototype-board interconnections, without first removing power. Any of the mode switch settings can be altered with power applied, but often it will be necessary to press RESET to ensure that the new mode is correctly adopted by the processor. A special reminder: The 0MHz speed enables single-stepping, so if you want the processor to work normally ensure that the clock setting is not at 0MHz!
An oscilloscope with at least two channels is required. Use of x10 probes is recommended. Measurements will be made using a processor clock frequency of 1MHz so, for faithful observation of the bus signals, the oscilloscope should have a bandwidth of at least 50MHz.
Use of the REB-hosted monitor program is essential. A terminal or terminal emulator with a serial interface capable of working at 19.2kBaud is required. The requirement is most conveniently met by a PC-based terminal emulator program. The Microsoft Windows `terminal' program is recommended.
Single instruction operation
The first observation involves seeing the processor performing one instruction continuously. The REB has a special mode for imposing a constant instruction on the processor:
(a) Apply power to the REB. The large switch at the centre of the left edge should have its toggle lifted, moved to the NOP position and released. The NOP led should light.
(b) Ensure that the speed is set to 1MHz on the bottom right rotary switch and then press RESET. After reset the processor will begin program excecution from location 0.
In constant instruction mode all memory and peripheral devices are disabled and so the bus will not be driven by them, irrespective of the addresses that the processor might issue. All the data bus lines are pulled high except for a few. The resulting pattern on the data bus is BF3FFFFF16.
(c) Examine the top 16 bits available on headers XD4 and XD3 using the tip of a scope probe and confirm that it corresponds to the top 16 bits of the constant instruction. Pin 1 (top left) of XD4 is the most significant data bus line, pin 2 (top right) is the next most significant and so on, zigzagging down the header. Details of these and other probe points are given in the appendix.
(d) Despite the title used on the switch, the instruction is not a No Operation instruction! Use your course notes to work out which instruction is represented by BF3FFFFF16. How many bus cycles would you expect it to take to execute?
(e) Identify and probe the SCK (System Clock) ball-headed test point amongst the others at the top right corner of the board. Confirm that this waveform is the clock waveform that you would expect.
(f) Using the EAn test points examine the address bus signals. Note that these signals are latched versions of the more transitory addresses that the processor issues in each cycle.
(g) Sketch the waveforms on EA2, EA3 and so on until you are sure that you understand the pattern being generated on the address bus. Your sketch should show the address waveforms arranged in rows with the same horizontal time axis. The oscilloscope must be sychronised to the same signal throughout to ensure that the time axes of all the traces are in step.
(h) Is the constant instruction being executed in the manner that you expected in (d)? What is the processor doing with the bus cycles you observe?
Simple program execution
Though the constant instruction mode is executing a program, it is not a very useful one. Next we allow the processor to execute a hand-compilation into SPARC machine code of the C function:
check1()
{
while (TRUE)
leds = switches;
}
i.e. a tight loop that replicates whatever pattern is set on the bottom row of toggle switches to the row of LEDs. There is no direct connection between the switches and the LEDs except via the processor bus. These input/output devices, like all such devices, are memory-mapped. They are accessed by the processor performing memory reads/writes to specific addresses. So to perform the copy the processor must first read the switches' address and then place the data that was read by writing to the LEDs' address. These addresses are SWITCH_ADDR (0008000416) and LED_ADDR (0008000016) respectively.
(a) Put the REB back into normal operational mode by lifting and moving the NOP switch into the up position. The NOP LED should extinguish. Move the EPROM image rotary switch to position 1. The LED image indicator 1 should light. Ensure that the clock switch is set to 1MHz and then press RESET.
(b) Check that the program is working by changing a few of the switch settings. Note that the switches have momentary action when pulled down and they latch when pushed up.
The assembler source for the code that should now be executing is:
Hex
Address Instruction
1000 SETHI %hi(LED_ADDR),R16
1004 L0: LDUB (R16+(SWITCH_ADDR-LED_ADDR)),R17
1008 STB R17,(R16+0)
100C BRA L0
1010 NOP
LDUB is load unsigned byte (i.e. load single byte without performing sign extension) and STB is store byte. %hi is a built-in assembler function that takes the high 22 bits of the argument. The addresses are byte addresses, since the SPARC is a byte-addressed machine (1004 is actually 0000100416).
(c) Using the same address waveform sketching technique as you used in the previous section, sketch sufficient of the EAn address lines to identify the cyclic pattern of the program. Also, sketch An (unlatched address bus found on connectors XA4-1), /HAL (not Hold Address Latch) or /ALE (not Address Latch Enable = / /HAL), /WE (not Write Enable) and RD (Read) lines. As before, use one of the bus signals to trigger the oscilloscope on one unique event within each iteration. This is to ensure that all the traces you sketch are in time sychronisation with each other. Alternatively you may find this much easier using the logic analyser.
(d) You will find that the addresses of the program will be interspersed with other addresses (ensure that you have a sketch of EA19 to differentiate the address groups). Using your sketched waveforms, identify what the processor is using each bus cycle for. In particular confirm that the write cycles follow the expected pattern shown in the appendix. Make sure you know how many cycles a write to external memory requires.
(e) Why is the `NOP' instruction being fetched? What is the special name for the instruction after a branch instruction? Is this instruction executed by the processor?
What you observe on the bus is only a part of what is going on inside the processor. An instruction pipeline is maintained by the processor in which several instructions are being processed. Each instruction moves through the following stages:
| Fetch | The instruction is fetched from program memory |
| Decode | The processor is set up to perform the actions specified in the instruction and computes the next instruction address |
| Execute | The action is carried out and the result held in temporary registers |
| Write | The result is written to the register or memory |
(f) In the light of this knowledge, further annotate each cycle of the constant instruction diagram of the previous section with the stages of execution of each instruction. The Fetch cycles are the ones actually observed, but one can imply what else is happening in the pipeline especially if any non-fetch instruction cycles occur.
(g) Further annotate your current address waveform sketch with the stages that each instruction is going through. It is clear when each instruction is being Fetched and the read and write cycles are clear, see if you can fill in the gaps. Unless something special happens to interrupt the pipeline flow, each instruction will progress through each stage in each cycle. (If you are not clear how to do this then ask for assistance.)
Further program execution
The EPROM image containing the program run in the previous section has no other reachable code as the processor jumps straight to it upon reset. Thus it is not possible to run any other programs without changing the EPROM (or its addressing, controlled by the REB IMAGE switch). In order to be able to run other fragments of code a supervisory program is required, typically called a Monitor. A monitor program is available in EPROM image 3. Using this will enable further small programs to be written and executed.
(a) Ensure that the SERA connector has a lead connected to a terminal or a PC running a terminal emulator program. Make sure that the terminal (program) is running and set up to transmit and receive serial data at 19.2kBaud. If using a terminal emulation program then ensure that the communications port addressed is that connected to the REB (e.g. COM2). Change the EPROM image rotary switch to position 3 and check that the clock speed is still set to 1MHz. Press RESET and the terminal should sign on and show the SPARC monitor program prompt >.
(b) Examine the bottom two locations in memory by using the Word inspection facilities of the monitor. Type the command (missing out the monitor > prompt but including the spaces between the characters):
> 2 w 0
followed by return. This means output the two words commencing at address 0. Using the SPARC instruction set data, decode what these instructions are. What is their purpose?
(c) A program can be executed by the making monitor calling it. Since the monitor is a program check that this works by using the command:
> call 0
This should cause the monitor to call the program at 0. This should restart the monitor.
(d) A copy of the program run in the previous section resides at the same address. You may confirm this by calling it:
> call 1000
and the switch to LED-copying behaviour should recommence. The processor is doing precisely the same actions as before so there is no way to get back to the monitor. The program does not acknowledge the existence of the monitor or any of the terminal access hardware, so it is oblivious to it.
(e) The only way to regain control using the monitor is to press RESET. Press RESET and then run an alternative version of the program by typing:
> call 1100
The program being executed achieves the same behaviour as the earlier one but is one instruction shorter. Its listing is:
Hex
Address Instruction
1100 SETHI %hi(LED_ADDR),R16
1104 L1: LDUB (R16+(SWITCH_ADDR-LED_ADDR)),R17
1108 BRA L1
110C STB R17,(R16+0)
(f) Using the same address bus signal sketching technique as before, find out how many clock cycles this program's loop takes to execute. Explain why it might be `more efficient' than the previous version of the program.
(g) Annotate each cycle with the internal stage of each instruction. You should find that the way the Load Unsigned Byte instruction has changed. Why has the behaviour of the same instruction changed in response to the other instructions around it?
Top View of the RISC Experimenter Board
LD Load integer instruction timing
ST Store integer instruction timing
Iain McNally
26-11-99