Microprocessor Systems - Exercise 1

A very simple single bus processor has been designed using Verilog Hardware Description Language.

The processor has a 16-bit data path and a 12-bit address space.

Each instruction is one word (16-bits) wide and consists of a 4-bit opcode and a 12-bit address operand:

The following instructions are supported:

Instruction	Opcode	Operation

  NOP		  0	No Operation
  JMP		  1	PC <= address
  JMPZ		  2	if (Z==1) then PC <= address
  JMPNZ		  3	if (Z==0) then PC <= address
  LDA		  4	Acc <= mem(address)
  ADD		  5	Acc <= Acc + mem(address)
  SUB		  6	Acc <= Acc - mem(address)
  AND		  7	Acc <= Acc & mem(address)
  OR		  8	Acc <= Acc | mem(address)
  NOT		  9	Acc <= ~Acc
  LSL		  10	Acc <= Acc << 1
  LSR		  11	Acc <= Acc >> 1
  STA		  15	mem(address) <= Acc

For this exercise you must investigate the behaviour of the design using the Verilog XL simulator. This advanced digital simulator allows you to track bus and register values as the simulated machine executes a machine code program.

Running the simulation

• Initialise your environment using the following command:

  	init_ups_simple
  

  this command will
  • create a working directory ~/design/verilog/ups/simple
  • copy the files library/processor.v, library/control.v, library/datapath.v, library/alu.v, library/memory.v, library/opcodes.v, multiply.v and system.v to that directory
  • open a new xterm window set to the correct directory (you will use this new xterm for the rest of the exercise)

• Simple Code

  • The following assembly language instructions are coded in the file library/memory.v:

            LDA    varX
    .loop   SUB   #1
            JMPZ  .done
            STA   varY
            ADD   varX
            STA   varX
            LDA   varY
            JMP   .loop
    .done   LDA   varX
            JMP   .end
    
    .end    JMP   .end
    

    where
    • varX is a variable stored at address 22 (varX has an initial value of 7)
    • varY is a variable stored at address 23
    • #1 is the constant value 1 stored at address 21

  • Using the following command, you can investigate the operation of the processor:

      verilog_xl -y library +libext+.v +incdir+library system.v
    

    The following figure is a snapshot of the simulation:

By stepping forwards and backwards through the simulation you should be able to observe the flow of the program listed above, including the update of memory locations and registers.

Which registers are updated during the Fetch state? Which registers are updated during the Execute state?

Can you relate the * symbol shown in the depiction of a multiplexor to the action of the multiplexor? Can you relate the * symbol shown in the depiction of a bus to the action of the bus? Can you follow the update of the Accumulator, based on the ALU function and the current state of the Accumulator and Data_bus?

For each of the first 20 clock cycles, you should record the values of the registers and memory variables. Then run through the same 20 clock cycles again - can you predict the update of registers and memory based on the information shown by the simulation?

Follow the simulation to it's conclusion - can you see what it is doing?