///////////////////////////////////////////////////////////////////////
//
// cpu_core module
//
///////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

module cpu_core( Data_out, Data_in, ENB, nME, ALE, RnW, nOE, SDO,
                 nIRQ, nWait, Clock, nReset, Test, SDI );

//
// I/O declarations
//

output [15:0] Data_out;
input [15:0] Data_in;

output ENB;
output nME, ALE, RnW, nOE, SDO;

input Clock, nReset, Test, SDI;
input nIRQ, nWait;

wire [3:0] Function;
wire [3:0] Opcode;

//
// This system doesn't simulate the scan path
//
assign SDO = SDI;

//
// This system is built from two smaller modules
//

control Control ( Function, SelInc, LoadPC, LoadIR,
                TrisOperand, TrisPC, TrisAcc, TrisMem,
                ENB, nME, ALE, RnW, nOE,
		Opcode, Zflag, nWait, Clock, nReset );

datapath Datapath ( Data_out, Data_in,
                Opcode, Zflag,
                Function, SelInc, LoadPC, LoadIR, 
                TrisOperand, TrisPC, TrisAcc, TrisMem,
                Clock, nReset );


endmodule