///////////////////////////////////////////////////////////////////////
//
// cpu module
//
//    this is simply a shell representing the pad_ring
//    which instances cpu_core
//
///////////////////////////////////////////////////////////////////////

`include "opcodes.v"
`timescale 1ns / 100ps

module cpu( Data, nME, ALE, RnW, nOE, SDO,
	nIRQ, nWait,
	Clock, nReset, Test, SDI );

//
// I/O declarations
//

inout [15:0] Data;
output nME, ALE, RnW, nOE, SDO;
input Clock, nReset, Test, SDI;
input nIRQ, nWait;

//
//wires
//
wire [15:0] Data_in;
wire [15:0] Data_out;
wire ENB;

//
// Simulation of bidirectional pads
//
assign Data = (ENB == 0) ? Data_out : 16'bz;
assign Data_in = Data;

cpu_core CPU_core ( 
	.Data_out(Data_out), .Data_in(Data_in),
	.ENB(ENB), .nME(nME), .ALE(ALE), .RnW(RnW), .nOE(nOE), .SDO(SDO),
	.nIRQ(nIRQ), .nWait(nWait),
	.Clock(Clock), .nReset(nReset), .Test(Test), .SDI(SDI) );

endmodule