`include "opcodes.v"
`timescale 1ns / 100ps

module alu( Zflag, Result, Reg, Mem, Function);

output [15:0] Result;
output Zflag;
input [15:0] Reg, Mem;
input [3:0] Function;

reg [15:0] Result;
wire Zflag;

   assign Zflag = (Result == 0);

   always @(Reg or Mem or Function)
      case (Function)
         `FnMem		: Result = Mem;
         `FnADD		: Result = Reg + Mem;
         `FnSUB		: Result = Reg - Mem;
         `FnAND		: Result = Reg & Mem;
         `FnOR		: Result = Reg | Mem;
         `FnNOT		: Result = ~Reg;
         `FnLSL		: Result = Reg << 1;
         `FnLSR		: Result = Reg >> 1;
         default	: Result = Reg;
      endcase

endmodule