`include "opcodes.v"
`timescale 1ns / 100ps

module system;

reg Clock, nReset;

processor Processor ( Clock, nReset);

always
  begin
     Clock = 0;
    #250
     Clock = 1;
    #500
     Clock = 0;
    #250
     Clock = 0;
  end

initial
  begin
     nReset = 0;
    #100
     nReset = 1;
  end

`include "monitor.v"

endmodule