Microprocessor Specification

Overview

• Task

  This year the task is to produce a microprocessor for embedded computing tasks. The processor should be as general purpose as possible.

• Functionality

  To demonstrate the usefulness of your design you will be asked to show that it can execute programs to perform the following tasks:

  • Factorial routine
  • Generation of pseudo-random numbers

• Strategy

  You may find that the resources for this project are rather less than those available to Intel in terms of:

  • Time
  • Manpower
  • Experience
  • Chip area

  For these reasons you should aim for the simplest design possible:

  • Small number of instructions
  • Small number of addressing modes
  • Simple instruction decoding
  • Simple architecture
  • Small number of registers
  • Simple instruction cycle
  • Minimum bus count
  • Highly bitsliced implementation

Constraints

• 16 bit architecture

  Your architecture should support a 16 bit wide datapath and a 2¹⁶ word address space.

• System Stack and Subroutines

  Your architecture should support subroutine call and return via a system stack. Your factorial program should use a recursive subroutine in order to demonstrate this facility. You should also support the use of the stack for parameter passing and local variable storage. A separate subroutine for multiplication (called by your factorial routine) should help to demonstrate these features.

  Note that a dedicated stack pointer is not required in order to support this system stack. A RISC processor would simply use one of its general purpose registers as a stack pointer. Nor is it necessary to provide auto-increment or auto-decrement in order to support stack pull(push). A RISC processor would typically use different instructions for load(store) data and increment(decrement) stack pointer. In order to support local variable storage on the stack you will need to include a simple indexed addressing mode.

• Six Register Limit

  Your processor should employ no more than six 16 bit registers, including the program counter and the instruction register. Solutions with between four and six registers are possible. This limit will help to keep processor sizes down and will encourage you to think carefully about the efficient use of the registers that you have.

• System compliance

  The system will consist of a central microprocessor (to be designed by you), connected via a single set of buses and some glue logic to ROM, RAM and I/O units.

As much as possible you are left to make your own decisions on the form of your design.

You should refer to any course notes or text books you have on the subject of microprocessor design in search of ideas (e.g. the early chapters of Computer Organization & Design - Patterson and Hennessy). Although your design may have more in common with microprocessors of the late '70s than with modern RISC machines, the same principles of good design apply. Remember that you are not competing with the UltraSPARC, only with the designs put forward by other MSc teams.

Memory Access

All memory accesses take four cycles of the system clock

• Address setup
• Address hold
• Data Setup
• Data Hold

• The nALE controls the address latch such that address is available through all four cycles.
• nME is gated in the Address decoder to provide separate nCE lines to each memory device. The nCE lines control the timing of data access operations.
• Common RnW and nOE lines control the direction of data transfer.

I/O information

Pad cells for this design will be taken from Alcatel Mietec's MTC35400 library for their 0.5um CMOS process. Alcatel provide us with empty abstract representations of these cells since the contents are considered company confidential. You will be provided with dummy versions of the cells which should simulate correctly using Magic and Verilog. To avoid design rule violations with the real pad cells you should keep routing wires one full design rule away from the edge of the pad cells except where connection is required.

The following types of pad are available:

The following pads will exist on the finished chip:

• Core power pads; 0Vcore, 3.3Vcore

• Pad ring power pads; 0Vpads, 3.3Vpads

  These pads make no direct connection to the core circuit. This will reduce switching noise on the core power rails.

• Input pads; Clock, nReset, Test, SDI

  These pads include a non-inverting buffer and static protection circuit.

• Output pads; RnW, nOE, nALE, nME, SDO

  These pads include non-inverting pad drivers.

• Bi-directional pads; Data[15:0]

  These pads include a tri-state non-inverting buffer (with inverted enable) on output and a non-inverting buffer on input. Three connections are made to the core of the cell in order to support a bi-directional pad. Although the pad connection is tri-state, the core connections are not, thus the ZI and A connections cannot be directly connected to the same internal bus.

Pinout