Declaration of Specialisms


Week 3 Week 4 Week 5 Week 6 Week 10 Week 12
Team Name Research Report

17 Feb
4:55pm

 Draft Design

18 Feb
12 noon

 Initial Design

24 Feb
4:55pm

 Behavioural Model
(4 instructions)

25 Feb
2 pm

 Behavioural Model

3 Mar
4:55pm

 Basic Datapath Simulation (ALU + Registers)

4 Mar
12 noon

 Cross Simulation

10 Mar
4:55pm

 Placed and Routed Control Unit Simulation

11 Mar
12 noon

 Design Submission

7 May
4:55pm

 Project Report

19 May
4:55pm
Instruction
Set		 Datapath
Diagram		 Instruction
Set		 Datapath
Diagram		 Verilog
Model		 Multiplication
Code		 Magic
Datapath		 Verilog
Control		 Design
Files		 Programmer's
Guide
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