Declaration of Specialisms


Week 3 Week 4 Week 5 Week 6 Week 8 Week 12
Team Name Research Report

16 Feb
4 pm

 Draft Design

17 Feb
12 noon

 Initial Design

23 Feb
4 pm

 Behavioural Model
(4 instructions)

24 Feb
2 pm

 Behavioural Model

2 Mar
4 pm

 Basic Datapath Simulation (ALU + Registers)

3 Mar
12 noon

 Cross Simulation

9 Mar
4 pm

 Placed and Routed Control Unit Simulation

10 Mar
12 noon

 Design Submission

25 March
4 pm

 Project Report

18 May
4 pm
Instruction
Set		 Datapath
Diagram		 Instruction
Set		 Datapath
Diagram		 Verilog
Model		 Multiplication
Code		 Magic
Datapath		 Verilog
Control		 Design
Files		 Programmer's
Guide
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