ncverilog: 09.20-s022: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
TOOL:	ncverilog	09.20-s022: Started on Apr 30, 2012 at 20:37:00 BST
ncverilog
	-sv
	-y
	example_nointerrupt
	-y
	system
	+libext+.sv
	+incdir+example_nointerrupt
	example_nointerrupt/opcodes.svh
	system/system.sv
	+define+prog_file="example_nointerrupt/prog.hex"
file: example_nointerrupt/opcodes.svh
	package worklib.opcodes:svh
		errors: 0, warnings: 0
file: system/system.sv
	module worklib.system:sv
		errors: 0, warnings: 0
file: system/cpu.sv
	module system.cpu:sv
		errors: 0, warnings: 0
file: system/cpu.sv
file: system/demux_bus.sv
	interface system.demux_bus:sv
		errors: 0, warnings: 0
file: system/decoder.sv
	module system.decoder:sv
		errors: 0, warnings: 0
file: system/ram.sv
	module system.ram:sv
		errors: 0, warnings: 0
file: system/io_leds.sv
	module system.io_leds:sv
		errors: 0, warnings: 0
file: system/io_switches.sv
	module system.io_switches:sv
		errors: 0, warnings: 0
file: system/io_timer.sv
	module system.io_timer:sv
		errors: 0, warnings: 0
file: system/io_serial.sv
	module system.io_serial:sv
		errors: 0, warnings: 0
file: example_nointerrupt/cpu_core.sv
	module example_nointerrupt.cpu_core:sv
		errors: 0, warnings: 0
file: example_nointerrupt/cpu_core.sv
file: example_nointerrupt/control.sv
	module example_nointerrupt.control:sv
		errors: 0, warnings: 0
file: example_nointerrupt/datapath.sv
	module example_nointerrupt.datapath:sv
		errors: 0, warnings: 0
file: example_nointerrupt/datapath.sv
file: example_nointerrupt/alu.sv
	module example_nointerrupt.alu:sv
		errors: 0, warnings: 0
		Caching library 'system' ....... Done
		Caching library 'worklib' ....... Done
		Caching library 'example_nointerrupt' ....... Done
	Elaborating the design hierarchy:
	Building instance overlay tables: .................... Done
	Generating native compiled code:
		example_nointerrupt.alu:sv <0x320186fc>
			streams:   2, words:   747
		example_nointerrupt.control:sv <0x77a413dd>
			streams:  19, words:  6588
		example_nointerrupt.cpu_core:sv <0x40e48e64>
			streams:   0, words:     0
		example_nointerrupt.datapath:sv <0x64e8a0bb>
			streams:  15, words:  4123
		system.cpu:sv <0x30a9c8eb>
			streams:   6, words:  1289
		system.decoder:sv <0x05392964>
			streams:   2, words:  1109
		system.demux_bus:sv <0x2bbb99b2>
			streams:  34, words: 35022
		system.io_leds:sv <0x20c4019f>
			streams:   4, words:  2386
		system.io_serial:sv <0x63a0f47c>
			streams:  21, words:  8288
		system.io_switches:sv <0x6ec3fc71>
			streams:   4, words:  1192
		system.io_timer:sv <0x75d9be32>
			streams:  33, words:  8789
		system.ram:sv <0x4d176888>
			streams:   7, words:  3213
		worklib.system:sv <0x1105959d>
			streams:  23, words:  8147
	Loading native compiled code:     .................... Done
	Building instance specific data structures.
	Design hierarchy summary:
		                   Instances  Unique
		Modules:                  12      12
		Interfaces:                1       1
		Verilog packages:          1       1
		Resolved nets:             0       2
		Registers:               152     152
		Scalar wires:             85       -
		Vectored wires:           34       -
		Always blocks:            30      30
		Initial blocks:           26      26
		Cont. assignments:        49      68
		Pseudo assignments:        6       6
		Simulation timescale:  100ps
	Writing initial simulation snapshot: worklib.system:sv
Loading snapshot worklib.system:sv .................... Done
ncsim> source /opt/cad/soft/cadence/ius/tools/inca/files/ncsimrc
ncsim> run
              383020:   LED update:    28
Terminating at address 99

Simulation stopped via $stop(1) at time 395020 NS + 3
./example_nointerrupt/monitor.sv:16          $stop;
ncsim> exit
TOOL:	ncverilog	09.20-s022: Exiting on Apr 30, 2012 at 20:37:10 BST  (total: 00:00:10)