///////////////////////////////////////////////////////////////////////
//
// ram module
//            2048 words.	0-2047
//
//
///////////////////////////////////////////////////////////////////////

`ifdef prog_file
  // already defined - do nothing
`else
  `define prog_file  "program.hex"
`endif

`ifdef ram_access_time
  // already defined - do nothing
`else
  `define ram_access_time 500ns
`endif


module ram(
  output wire nWait,
  inout [15:0] Data,
  input [10:0] Address,
  input nOE, RnW, nCE
  );

timeunit 1ns;
timeprecision 100ps;

specify
  specparam tViolate=250;
  $width(negedge nCE, tViolate);
  $width(posedge nCE, tViolate);
  $width(negedge RnW &&& ~nCE, tViolate);
  $width(posedge RnW &&& ~nCE, tViolate);
  $setuphold(edge[10, 01] nCE, Address, tViolate, tViolate);
  $setuphold(edge[10, 01] nCE, RnW, tViolate, tViolate);
  $setuphold(edge[10, 01] nCE, nOE, tViolate, tViolate);
  $setuphold(edge[01] nCE &&& ~RnW, Data, tViolate, tViolate);
endspecify

logic [15:0] Data_stored [ 0 : 2047 ];
logic delay;

initial
  delay = 0;

always @(negedge nCE or Address)
  if (! nCE)
    begin
      delay = 1;
      #`ram_access_time
      delay = 0;
    end 

assign nWait = (delay && !nCE && (!nOE || !RnW)) ? 0 : 1'bz;

initial
  #1ns // This delay allows for program file to
       // be written within the same simulation
       $readmemh(`prog_file,Data_stored);

assign Data =
          ((nOE == 0) && (RnW == 1) && (nCE == 0) && (delay == 0)) ?
					Data_stored [Address] : 16'bz;

always @(nCE or RnW)
  begin
    while ((nCE == 0) && (RnW == 0))
      begin
         Data_stored [Address] = Data;
        @(nCE or RnW or Address or Data);
      end
  end


endmodule