ncverilog: 09.20-s022: (c) Copyright 1995-2010 Cadence Design Systems, Inc. TOOL: ncverilog 09.20-s022: Started on Jul 28, 2011 at 16:43:50 BST ncverilog -sv +gui +ncaccess+r -y synthesized -y system -y /opt/cad/bim/fcdeCells/verilog/behavioural +libext+.sv +incdir+synthesized synthesized/definitions.svh system/system.sv programs/program.sv +define+prog_file=\"programs/program.hex\" +define+no_state_view +nctimescale+1ns/100ps -s Recompiling... reason: file './synthesized/monitor.sv' is newer than expected. expected: Thu Jul 28 16:38:42 2011 actual: Thu Jul 28 16:43:25 2011 file: synthesized/definitions.svh file: system/system.sv module worklib.system:sv errors: 0, warnings: 0 file: programs/program.sv file: system/cpu.sv file: system/cpu.sv file: system/addlatch.sv file: system/decoder.sv file: system/ram.sv file: system/io_leds.sv file: system/io_switches.sv file: system/io_timer.sv file: system/io_serial.sv file: synthesized/cpu_core.sv file: synthesized/cpu_core.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/inv.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/and2.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/nor2.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/nand3.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/nand4.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/mux2.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/nand2.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/xor2.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/scandtype.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/scanreg.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/trisbuf.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/fulladder.sv file: /opt/cad/bim/fcdeCells/verilog/behavioural/buffer.sv Caching library 'behavioural' ....... Done Caching library 'system' ....... Done Caching library 'worklib' ....... Done Caching library 'synthesized' ....... Done Elaborating the design hierarchy: ncelab: *W,CUTSTL: Design unit 'xor2' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'trisbuf' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'scanreg' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'scandtype' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'nor2' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'nand4' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'nand3' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'nand2' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'mux2' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'inv' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'fulladder' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'buffer' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. ncelab: *W,CUTSTL: Design unit 'and2' contains SystemVerilog time literals and does not have an applicable `timescale directive. Further, an option to set the timescale has been supplied to the elaborator. Due to a temporary implementation limitation concerning this scenario, any delays involving these SystemVerilog time literals may be incorrectly scaled. Building instance overlay tables: .................... Done Generating native compiled code: worklib.system:sv <0x1de1c0f8> streams: 38, words: 21713 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 464 24 Verilog packages: 1 1 Primitives: 2 1 Registers: 123 78 Scalar wires: 605 - Expanded wires: 112 7 Vectored wires: 12 - Always blocks: 65 20 Initial blocks: 11 11 Cont. assignments: 358 53 Pseudo assignments: 6 6 Timing checks: 232 81 Simulation timescale: 100ps Writing initial simulation snapshot: worklib.system:sv ncsim> ncsim> source /opt/cad/soft/cadence/ius/tools/inca/files/ncsimrc ncsim> ------------------------------------- Relinquished control to SimVision... # Restoring simulation environment... ncsim> input -quiet .reinvoke.sim ncsim> file delete .reinvoke.sim ncsim> run 383020: LED update: 28 Terminating at address 99 Simulation stopped via $stop(1) at time 393 US + 0 ncsim> ...Regained control from SimVision ------------------------------------- ncsim> ncsim: *W,CMUSEX: Control-D in interactive input - one more to exit. ncsim> exit TOOL: ncverilog 09.20-s022: Exiting on Jul 29, 2011 at 13:55:35 BST (total: 21:11:45)