`timescale 1ns / 100ps
module and2 ( Y, A, B );

  output Y;
  input A, B;

  parameter delay = 1;

  assign #delay Y = &{A, B};

endmodule
module buffer ( Y, A );

  output Y;
  input A;

  parameter delay = 1;

  assign #delay Y = A;

endmodule
module fulladder ( S, Cout, A, B, Cin );

  output S, Cout;
  input A, B, Cin;

  parameter delay = 1;

  assign #delay {Cout,S} = A + B + Cin;

endmodule
module halfadder ( S, C, A, B );

  output S, C;
  input A, B;

  parameter delay = 1;

  assign #delay S = ^{A, B};
  assign #delay C = &{A, B};

endmodule
module inv ( Y, A );

  output Y;
  input A;

  parameter delay = 1;

  assign #delay Y = !A;

endmodule
module mux2 ( Y, I0, I1, S );

  output Y;
  input I0, I1, S;

  parameter delay = 1;

  assign #delay Y = (!S && I0) || (S && I1);

endmodule
module nand2 ( Y, A, B );

  output Y;
  input A, B;

  parameter delay = 1;

  assign #delay Y = ! ( &{A, B} );

endmodule
module nand3 ( Y, A, B, C );

  output Y;
  input A, B, C;

  parameter delay = 1;

  assign #delay Y = ! ( &{A, B, C} );

endmodule
module nand4 ( Y, A, B, C, D );

  output Y;
  input A, B, C, D;

  parameter delay = 1;

  assign #delay Y = ! ( &{A, B, C, D} );

endmodule
module nor2 ( Y, A, B );

  output Y;
  input A, B;

  parameter delay = 1;

  assign #delay Y = ! ( |{A, B} );

endmodule
module nor3 ( Y, A, B, C );

  output Y;
  input A, B, C;

  parameter delay = 1;

  assign #delay Y = ! ( |{A, B, C} );

endmodule
module or2 ( Y, A, B );

  output Y;
  input A, B;

  parameter delay = 1;

  assign #delay Y = |{A, B};

endmodule
module scandtype ( Q, nQ, D, Clock, nReset );

  output Q, nQ;
  input D, Clock, nReset;
  
  parameter delay=20;

  specify
    // T_setup = 25x100ps
    // T_hold  =  2x100ps
    $setuphold(posedge Clock, D, 25, 2);
  endspecify

  reg Q;

  always @(posedge Clock or negedge nReset)
    if (!nReset)
      Q = 0;
    else
      Q = #delay D;

  assign nQ = !Q;

endmodule
module scanreg ( Q, nQ, D, Load, Clock, nReset );

  output Q, nQ;
  input D, Load, Clock, nReset;

  parameter delay=20;

  specify
    // T_setup = 25x100ps
    // T_hold  =  2x100ps
    $setuphold(posedge Clock, D, 25, 2);
  endspecify

  reg Q;

  always @(posedge Clock or negedge nReset)
    if (!nReset)
      Q = 0;
    else
      if (Load) Q = #delay D;

  assign nQ = !Q;

endmodule
module trisbuf ( Y, A, Enable );

  output Y;
  input A, Enable;

  parameter delay = 1;

  assign #delay Y = (Enable) ? A : 1'bz;

endmodule
module xor2 ( Y, A, B );

  output Y;
  input A, B;

  parameter delay=1;
  
  assign #delay Y = ^{A, B};

endmodule