ncverilog: 09.20-s022: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
TOOL:	ncverilog	09.20-s022: Started on Jul 27, 2011 at 23:13:02 BST
ncverilog
	-sv
	definitions.svh
	datapath.sv
	alu.sv
	cpu_core.sv
	control.sv
file: definitions.svh
	package worklib.definitions:svh
		errors: 0, warnings: 0
file: datapath.sv
	module worklib.datapath:sv
		errors: 0, warnings: 0
file: alu.sv
	module worklib.alu:sv
		errors: 0, warnings: 0
file: cpu_core.sv
	module worklib.cpu_core:sv
		errors: 0, warnings: 0
file: control.sv
	module worklib.control:sv
		errors: 0, warnings: 0
		Caching library 'worklib' ....... Done
	Elaborating the design hierarchy:
	Building instance overlay tables: .................... Done
	Generating native compiled code:
		worklib.alu:sv <0x7ea47669>
			streams:   2, words:   221
		worklib.control:sv <0x56073880>
			streams:  18, words:  1509
		worklib.cpu_core:sv <0x39e6bb87>
			streams:   2, words:    61
		worklib.datapath:sv <0x01d33f08>
			streams:  15, words:  1052
	Loading native compiled code:     .................... Done
	Building instance specific data structures.
	Design hierarchy summary:
		                   Instances  Unique
		Modules:                   4       4
		Verilog packages:          1       1
		Resolved nets:             0       1
		Registers:                25      25
		Scalar wires:             28       -
		Vectored wires:           16       -
		Always blocks:             3       3
		Cont. assignments:        13      25
		Pseudo assignments:        4       4
		Simulation timescale:  100ps
	Writing initial simulation snapshot: worklib.cpu_core:sv
Loading snapshot worklib.cpu_core:sv .................... Done
ncsim> source /opt/cad/soft/cadence/ius/tools/inca/files/ncsimrc
ncsim> run
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
TOOL:	ncverilog	09.20-s022: Exiting on Jul 27, 2011 at 23:13:04 BST  (total: 00:00:02)