///////////////////////////////////////////////////////////////////////
//
// system module
//
//    this is the top-level module which describes the complete system
//
///////////////////////////////////////////////////////////////////////

`include "opcodes.sv"

module system;

timeunit 1ns;
timeprecision 100ps;

import definitions::*;

logic Clock, nReset, Test, SDI;
logic nMEi, ALEi, RnWi, nOEi;
logic [15:0] switches;

wire [15:0] LEDs;
wire [15:0] Address;
wire [15:0] Data;

wire ALE, nME, nOE, RnW, nIRQ, nWait;

pullup (weak1) (nIRQ);
pullup (weak1) (nWait);

cpu CPU ( .Data(Data), .nME(nME), .ALE(ALE), .RnW(RnW), .nOE(nOE), .SDO(SDO),
  .nIRQ(nIRQ), .nWait(nWait),
  .Clock(Clock), .nReset(nReset), .Test(Test), .SDI(SDI)  );

addlatch AddLatch
  (  Address, Data, ALEi );
decoder Decoder
  ( nSelRAM, nSelLED, nSelSwitch, nSelTimer, nSelSerial, Address, nMEi );
ram RAM
  ( nWait, Data, Address[10:0], nOEi, RnWi, nSelRAM );
io_leds IO_LEDS
  ( LEDs, nWait, Data, RnWi, nSelLED );
io_switches IO_SWITCHES
  ( nWait, Data, switches, nOEi, nSelSwitch);
io_timer IO_TIMER
  ( nIRQ, nWait, Data, Address[1:0], nOEi, RnWi, nSelTimer, Clock, nReset );
io_serial IO_SERIAL
  ( nIRQ, nWait, Data, Address[0:0], nOEi, RnWi, nSelSerial, Clock, nReset );

`ifdef hold_signals_during_reset

  always @(Test or nReset)
  if (! nReset)
    begin
      nMEi = 1;
      ALEi = 0;
      RnWi = 1;
      nOEi = 1;
    end
  else if (Test == 0)
    begin
      assign nMEi = nME;
      assign ALEi = ALE;
      assign RnWi = RnW;
      assign nOEi = nOE;
    end
  else
    begin
      deassign nMEi;
      assign ALEi = 0; // keep address bus constant
      deassign RnWi;
      assign nOEi = 1;// mem should not drive data bus
    end

`else

  always @(Test)
  if (Test == 0)
    begin
      assign nMEi = nME;
      assign ALEi = ALE;
      assign RnWi = RnW;
      assign nOEi = nOE;
    end
  else
    begin
      deassign nMEi;
      assign ALEi = 0; // keep address bus constant
      deassign RnWi;
      assign nOEi = 1;// mem should not drive data bus
    end

`endif

`ifdef special_stimulus

  `include "stimulus.sv"

`else

  initial
    begin
       Clock = 0;
       nReset = 0;
      #250ns
       nReset = 1;
      #500ns
       while ( 1 )
          begin
             Clock = 0;
            #250ns
             Clock = 1;
            #500ns
             Clock = 0;
            #250ns
             Clock = 0;
          end
    end

  initial
    begin
      `ifdef switch_value
        switches = `switch_value;
      `else
         switches = 1;
      `endif
      Test = 0;
      SDI = 0;
    end
  
`endif

`ifdef special_monitor

  `include "monitor.sv"

`endif

`ifdef sim_time

  initial
    begin
      #`sim_time
      $stop;
      $finish;
    end

`endif

endmodule