///////////////////////////////////////////////////////////////////////
//
// demux_bus interface
//
//    this interface describes the signals in the demultiplexed bus
//
///////////////////////////////////////////////////////////////////////

`include "options.sv"

interface demux_bus(
  output nIRQ,
  output nWait,
  inout [15:0] Data,
  output logic [15:0] Address,
  input uP_ALE,
  input uP_nME,
  input uP_nOE,
  input uP_RnW,
  input Test,
  input nReset
  );

timeunit 1ns;
timeprecision 100ps;

logic ALE, nME, nOE, RnW;

// Define the connections for the Bus Slaves (no nIRQ connection)
modport Slave (
  inout Data,
  input Address, nOE, RnW,
  output nWait
);

// Define the connections for the Bus Slaves which drive nIRQ
modport InterruptSlave (
  inout Data,
  input Address, nOE, RnW,
  output nIRQ, nWait
);

// Define the connections for the Address Decoder
modport AddressDecode (
  input Address, nME
);

// Define the connections for the Bus Watch module
modport Observer (
  input Data, Address,
  input ALE, nME, nOE, RnW,
  input nIRQ, nWait
  );

// Define the logic for the Address Latch
always_latch
  if (ALE == 1)
    Address = Data;

// Define the logic for nIRQ and nWait pull-up 
wire (weak1,weak0) nIRQ_pullup = 1;
assign nIRQ = nIRQ_pullup;
wire (weak1,weak0) nWait_pullup = 1;
assign nWait = nWait_pullup;

`ifdef hold_signals_during_reset

  always @(Test or nReset)
  if (! nReset)
    begin
      nME = 1;
      ALE = 0;
      RnW = 1;
      nOE = 1;
    end
  else if (Test == 0)
    begin
      assign nME = uP_nME;
      assign ALE = uP_ALE;
      assign RnW = uP_RnW;
      assign nOE = uP_nOE;
    end
  else
    begin
      deassign nME;
      assign ALE = 0; // keep address bus constant
      deassign RnW;
      assign nOE = 1;// mem should not drive data bus
    end

`else

  always @(Test)
  if (Test == 0)
    begin
      assign nME = uP_nME;
      assign ALE = uP_ALE;
      assign RnW = uP_RnW;
      assign nOE = uP_nOE;
    end
  else
    begin
      deassign nME;
      assign ALE = 0; // keep address bus constant
      deassign RnW;
      assign nOE = 1;// mem should not drive data bus
    end

`endif


endinterface