ncverilog: 09.20-s022: (c) Copyright 1995-2010 Cadence Design Systems, Inc. TOOL: ncverilog 09.20-s022: Started on Mar 30, 2012 at 12:34:48 BST ncverilog -sv +gui +ncaccess+r -y example -y system +libext+.sv +incdir+example example/opcodes.svh system/system.sv +define+prog_file="example/prog.hex" -s Recompiling... reason: file './system/system.sv' is newer than expected. expected: Fri Mar 30 12:30:22 2012 actual: Fri Mar 30 12:33:33 2012 file: example/opcodes.svh file: system/system.sv module worklib.system:sv errors: 0, warnings: 0 file: system/cpu.sv file: system/cpu.sv file: system/demux_bus.sv file: system/bus_watch.sv file: system/decoder.sv file: system/ram.sv file: system/io_leds.sv file: system/io_switches.sv file: system/io_timer.sv file: system/io_serial.sv file: example/cpu_core.sv file: example/cpu_core.sv file: example/control.sv file: example/datapath.sv file: example/datapath.sv file: example/alu.sv Caching library 'system' ....... Done Caching library 'worklib' ....... Done Caching library 'example' ....... Done Elaborating the design hierarchy: Building instance overlay tables: .................... Done Generating native compiled code: system.bus_watch:sv <0x31e9f23f> streams: 7, words: 1725 system.decoder:sv <0x49938bd0> streams: 2, words: 1189 system.demux_bus:sv <0x6eb2f6d5> streams: 9, words: 7650 system.io_leds:sv <0x05bc00db> streams: 4, words: 2527 system.io_serial:sv <0x23599a43> streams: 23, words: 9002 system.io_switches:sv <0x612ebeca> streams: 4, words: 1237 system.io_timer:sv <0x56ba1ffd> streams: 34, words: 9333 system.ram:sv <0x58f89193> streams: 7, words: 3258 worklib.system:sv <0x339e83b5> streams: 23, words: 16292 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 13 13 Interfaces: 1 1 Verilog packages: 1 1 Resolved nets: 0 2 Registers: 125 125 Scalar wires: 95 - Expanded wires: 32 2 Vectored wires: 34 - Always blocks: 22 22 Initial blocks: 10 10 Cont. assignments: 62 78 Pseudo assignments: 7 7 Timing checks: 106 36 Simulation timescale: 100ps Writing initial simulation snapshot: worklib.system:sv ncsim> ncsim> source /opt/cad/soft/cadence/ius/tools/inca/files/ncsimrc ncsim> ------------------------------------- Relinquished control to SimVision... # Restoring simulation environment... ncsim> input {example/system.tcl} ncsim> ncsim> # system.tcl ncsim> ncsim> database -open waves.shm -default Created default SHM database waves.shm ncsim> ncsim> simvision { > > source /opt/cad/bim/fcde/tcl/routines.tcl > source /opt/cad/bim/fcde/tcl/read_fig.tcl > > ecsWaves { > system.Clock > system.nReset > system.ALE > system.nME > system.nOE > system.RnW > system.nWait > system.Data > system.Address > } "Waves for Example uP Design" > > ecsRegisters { > > system.RAM.Data_stored[000] > system.RAM.Data_stored[001] > system.RAM.Data_stored[002] > system.RAM.Data_stored[003] > system.RAM.Data_stored[004] > system.RAM.Data_stored[005] > system.RAM.Data_stored[006] > system.RAM.Data_stored[007] > system.RAM.Data_stored[008] > system.RAM.Data_stored[009] > system.RAM.Data_stored[010] > system.RAM.Data_stored[011] > system.RAM.Data_stored[012] > system.RAM.Data_stored[013] > system.RAM.Data_stored[014] > system.RAM.Data_stored[015] > system.RAM.Data_stored[016] > system.RAM.Data_stored[017] > system.RAM.Data_stored[018] > system.RAM.Data_stored[019] > system.RAM.Data_stored[020] > system.RAM.Data_stored[021] > system.RAM.Data_stored[022] > system.RAM.Data_stored[023] > system.RAM.Data_stored[024] > system.RAM.Data_stored[025] > system.RAM.Data_stored[026] > system.RAM.Data_stored[027] > system.RAM.Data_stored[028] > system.RAM.Data_stored[029] > system.RAM.Data_stored[030] > system.RAM.Data_stored[031] > system.RAM.Data_stored[032] > system.RAM.Data_stored[033] > system.RAM.Data_stored[034] > system.RAM.Data_stored[035] > system.RAM.Data_stored[036] > system.RAM.Data_stored[037] > system.RAM.Data_stored[038] > system.RAM.Data_stored[039] > system.RAM.Data_stored[040] > system.RAM.Data_stored[041] > system.RAM.Data_stored[042] > system.RAM.Data_stored[043] > system.RAM.Data_stored[044] > system.RAM.Data_stored[045] > system.RAM.Data_stored[046] > system.RAM.Data_stored[047] > system.RAM.Data_stored[048] > system.RAM.Data_stored[049] > } "Registers for Example uP Design" "Memory" > > if { [file exists $::env(LIB)/system.fig] == 1 } { > ecsReadFig $::env(LIB)/system.fig "Registers for Example uP Design" "Architecture" > } elseif { [file exists $::env(SYS)/system.fig] == 1 } { > ecsReadFig $::env(SYS)/system.fig "Default Registers for uP Designs" "Architecture" > } > > # ========================================================================= > # Register Window > > # Open new register window > > window new RegisterWindow -name "Memory View for Example uP Design" > window geometry "Memory View for Example uP Design" 700x450+0+350 > register using "Memory View for Example uP Design" > > # Add signal values (specified location and format) > > # ========================================================================= > > register addtype -type text -x0 10 -y0 15 -text {Memory (code)} \ > -fill red > > register addtype -type text -x0 10 -y0 40 -text {[0]} > register addtype -type signalvalue -x0 40 -y0 40 -radix %x \ > {system.RAM.Data_stored[0]} > register addtype -type signalvalue -x0 100 -y0 40 -radix %s \ > {system.DisassemblyListing[0]} > > register addtype -type text -x0 10 -y0 60 -text {[1]} > register addtype -type signalvalue -x0 40 -y0 60 -radix %x \ > {system.RAM.Data_stored[1]} > register addtype -type signalvalue -x0 100 -y0 60 -radix %s \ > {system.DisassemblyListing[1]} > > register addtype -type text -x0 10 -y0 80 -text {[2]} > register addtype -type signalvalue -x0 40 -y0 80 -radix %x \ > {system.RAM.Data_stored[2]} > register addtype -type signalvalue -x0 100 -y0 80 -radix %s \ > {system.DisassemblyListing[2]} > > register addtype -type text -x0 10 -y0 100 -text {[3]} > register addtype -type signalvalue -x0 40 -y0 100 -radix %x \ > {system.RAM.Data_stored[3]} > register addtype -type signalvalue -x0 100 -y0 100 -radix %s \ > {system.DisassemblyListing[3]} > > register addtype -type text -x0 10 -y0 120 -text {[4]} > register addtype -type signalvalue -x0 40 -y0 120 -radix %x \ > {system.RAM.Data_stored[4]} > register addtype -type signalvalue -x0 100 -y0 120 -radix %s \ > {system.DisassemblyListing[4]} > > register addtype -type text -x0 10 -y0 140 -text {[5]} > register addtype -type signalvalue -x0 40 -y0 140 -radix %x \ > {system.RAM.Data_stored[5]} > register addtype -type signalvalue -x0 100 -y0 140 -radix %s \ > {system.DisassemblyListing[5]} > > register addtype -type text -x0 10 -y0 160 -text {[6]} > register addtype -type signalvalue -x0 40 -y0 160 -radix %x \ > {system.RAM.Data_stored[6]} > register addtype -type signalvalue -x0 100 -y0 160 -radix %s \ > {system.DisassemblyListing[6]} > > register addtype -type text -x0 10 -y0 180 -text {[7]} > register addtype -type signalvalue -x0 40 -y0 180 -radix %x \ > {system.RAM.Data_stored[7]} > register addtype -type signalvalue -x0 100 -y0 180 -radix %s \ > {system.DisassemblyListing[7]} > > register addtype -type text -x0 10 -y0 200 -text {[8]} > register addtype -type signalvalue -x0 40 -y0 200 -radix %x \ > {system.RAM.Data_stored[8]} > register addtype -type signalvalue -x0 100 -y0 200 -radix %s \ > {system.DisassemblyListing[8]} > > register addtype -type text -x0 10 -y0 220 -text {[9]} > register addtype -type signalvalue -x0 40 -y0 220 -radix %x \ > {system.RAM.Data_stored[9]} > register addtype -type signalvalue -x0 100 -y0 220 -radix %s \ > {system.DisassemblyListing[9]} > > register addtype -type text -x0 10 -y0 240 -text {[10]} > register addtype -type signalvalue -x0 40 -y0 240 -radix %x \ > {system.RAM.Data_stored[10]} > register addtype -type signalvalue -x0 100 -y0 240 -radix %s \ > {system.DisassemblyListing[10]} > > register addtype -type text -x0 10 -y0 260 -text {[11]} > register addtype -type signalvalue -x0 40 -y0 260 -radix %x \ > {system.RAM.Data_stored[11]} > register addtype -type signalvalue -x0 100 -y0 260 -radix %s \ > {system.DisassemblyListing[11]} > > register addtype -type text -x0 10 -y0 290 -text {[99]} > register addtype -type signalvalue -x0 40 -y0 290 -radix %x \ > {system.RAM.Data_stored[99]} > register addtype -type signalvalue -x0 100 -y0 290 -radix %s \ > {system.DisassemblyListing[99]} > > # ========================================================================= > register addtype -type line -x0 250 -y0 0 -x1 250 -y1 300 \ > -fill green > # ========================================================================= > > register addtype -type text -x0 260 -y0 15 \ > -text {Memory (constants)} -fill red > > register addtype -type text -x0 260 -y0 40 -text {[20]} > register addtype -type signalvalue -x0 310 -y0 40 -radix %d \ > {system.RAM.Data_stored[20]} > register addtype -type text -x0 260 -y0 60 -text {[21]} > register addtype -type signalvalue -x0 310 -y0 60 -radix %d \ > {system.RAM.Data_stored[21]} > > # ========================================================================= > register addtype -type line -x0 450 -y0 0 -x1 450 -y1 300 \ > -fill green > # ========================================================================= > > register addtype -type text -x0 460 -y0 15 -text {Memory (data)} \ > -fill red > > register addtype -type text -x0 460 -y0 40 -text {[256]} > register addtype -type signalvalue -x0 510 -y0 40 -radix %d \ > {system.RAM.Data_stored[256]} > register addtype -type text -x0 460 -y0 60 -text {[257]} > register addtype -type signalvalue -x0 510 -y0 60 -radix %d \ > {system.RAM.Data_stored[257]} > register addtype -type text -x0 460 -y0 80 -text {[258]} > register addtype -type signalvalue -x0 510 -y0 80 -radix %d \ > {system.RAM.Data_stored[258]} > register addtype -type text -x0 460 -y0 100 -text {[259]} > register addtype -type signalvalue -x0 510 -y0 100 -radix %d \ > {system.RAM.Data_stored[259]} > > } ncsim> ncsim> # ========================================================================= ncsim> # Probe ncsim> ncsim> # Any signals included in register window but not in waveform window ncsim> # should be probed ncsim> ncsim> probe -create -shm system.RAM.Data_stored Created probe 1 ncsim> probe -create -shm system.DisassemblyListing Created probe 2 ncsim> # ========================================================================= ncsim> input -quiet .reinvoke.sim ncsim> file delete .reinvoke.sim ncsim> probe -create -shm system.Clock system.nReset system.ALE system.nME system.nOE system.RnW system.nWait system.Data system.Address Created probe 28 ncsim> probe -create -shm system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored system.RAM.Data_stored Created probe 29 ncsim> reset Loaded snapshot worklib.system:sv ncsim> probe -create -shm system.CPU.CPU_core.Opcode system.CPU.CPU_core.Zflag system.CPU.CPU_core.Datapath.ACC system.CPU.CPU_core.Datapath.PC system.CPU.CPU_core.Datapath.IR system.Address system.Zero_text system.WR_text system.Access_text system.Function_text system.nME system.nOE system.RnW system.CPU.CPU_core.TrisAcc system.CPU.CPU_core.TrisPC system.CPU.CPU_core.TrisOperand system.CPU.CPU_core.LoadPC system.CPU.CPU_core.LoadIR system.CPU.CPU_core.SelInc system.CPU.CPU_core.TrisMem system.CPU.CPU_core.ENB system.ALE system.nIRQ system.Data system.switches system.LEDs system.CPU.CPU_core.Datapath.SysBus system.CPU.CPU_core.Control.state system.OpMnemonic_text system.AdMode_text system.CPU.CPU_core.Control.sub_state system.CPU.CPU_core.Datapath.Operand Created probe 30 ncsim> run 383020: LED update: 28 Terminating at address 99 Simulation stopped via $stop(1) at time 395020 NS + 3 ncsim> ^C ncsim> exit TOOL: ncverilog 09.20-s022: Exiting on Mar 30, 2012 at 12:40:13 BST (total: 00:05:25)