`include "opcodes.sv"

module datapath( SysBus, Data_in,
                 Opcode, Zflag,
                 Function, SelInc, LoadPC, LoadIR, 
                 TrisOperand, TrisPC, TrisAcc, TrisMem,
                 Clock, nReset );

output [15:0] SysBus;
input  [15:0] Data_in;
output [3:0] Opcode;
output Zflag;
input  [3:0] Function;
input  SelInc, LoadPC, LoadIR, TrisOperand, TrisPC, TrisAcc, TrisMem;
input  Clock, nReset;

reg  [15:0] IR, ACC;
reg  [11:0] PC;
wire [15:0] ALU_output;
wire [11:0] Operand, PC_mux_output;

//
// ALU Instance
//
   alu ALU ( Zflag, ALU_output, ACC, SysBus, Function);

//
// Divide instruction into Opcode and Operand
//
   assign Opcode  = IR[15:12];
   assign Operand = IR[11:0];

//
// Drive SysBus as required
// (Operand and PC values are "zero extended" to give 16 bits)
//
   assign SysBus = (TrisOperand) ? {4'b0,Operand} : 16'bz;
   assign SysBus = (TrisPC)      ? {4'b0,PC}      : 16'bz;
   assign SysBus = (TrisAcc)     ? ACC            : 16'bz;
   assign SysBus = (TrisMem)     ? Data_in        : 16'bz;

//
// Multiplexor for PC update
//
   assign PC_mux_output = (SelInc) ? PC + 1 : Operand;

//
// Update Registers as required
//
   always_ff @(posedge Clock, negedge nReset)
      if (!nReset)
         begin
            ACC <= 0;
            IR  <= 0; // `NOP
            PC  <= 0;
	 end
      else
         begin
            ACC <= #20ns ALU_output;
            if (LoadIR) IR <= #20ns SysBus;
            if (LoadPC) PC <= #20ns PC_mux_output;
	 end
endmodule