`include "opcodes.sv"

module system;

reg Clock, nReset;

processor Processor ( Clock, nReset);

always
  begin
     Clock = 0;
    #250ns
     Clock = 1;
    #500ns
     Clock = 0;
    #250ns
     Clock = 0;
  end

initial
  begin
     nReset = 0;
    #100ns
     nReset = 1;
  end

`include "monitor.sv"

endmodule