`include "opcodes.sv"

module alu( Zflag, Result, ACC, Mem, Function);

output [15:0] Result;
output Zflag;
input [15:0] ACC, Mem;
input [3:0] Function;

reg [15:0] Result;
wire Zflag;

   assign Zflag = (ACC == 0);

   always_comb
      case (Function)
         `FnMem		: Result = Mem;
         `FnADD		: Result = ACC + Mem;
         `FnSUB		: Result = ACC - Mem;
         `FnAND		: Result = ACC & Mem;
         `FnOR		: Result = ACC | Mem;
         `FnNOT		: Result = ~ACC;
         `FnLSL		: Result = ACC << 1;
         `FnLSR		: Result = ACC >> 1;
         default	: Result = ACC;
      endcase

endmodule