`timescale 100ps / 10ps
module cpu(
	Data,
	nME, ALE, RnW, nOE, SDO,
	nIRQ, Clock, nReset, Test, SDI
	);

output  RnW, SDO, ALE, nME, nOE;

inout  [15:0] Data;

input  nIRQ, Clock, SDI, Test, nReset;

// include netlist information from cpu.vnet

`include "cpu.vnet"

endmodule