Netlist File

 # cpu.net
 #
 # **** This version supports nIRQ pin ****
 #
 # This file assumes single sub-module cpu_core (instance name cpu_core_0)
 # It also assumes Data_in/_out signals use square brackets for index values
 # The required labels within cpu_core are:
 #   Vdd!
 #   GND!
 #   Clock
 #   nReset
 #   Test
 #   SDI
 #   nIRQ
 #   SDO
 #   ALE
 #   nME
 #   nOE
 #   RnW
 #   Data_in[0]
 #   Data_in[1]
 #   Data_in[2]
 #   Data_in[3]
 #   Data_in[4]
 #   Data_in[5]
 #   Data_in[6]
 #   Data_in[7]
 #   Data_in[8]
 #   Data_in[9]
 #   Data_in[10]
 #   Data_in[11]
 #   Data_in[12]
 #   Data_in[13]
 #   Data_in[14]
 #   Data_in[15]
 #   Data_out[0]
 #   Data_out[1]
 #   Data_out[2]
 #   Data_out[3]
 #   Data_out[4]
 #   Data_out[5]
 #   Data_out[6]
 #   Data_out[7]
 #   Data_out[8]
 #   Data_out[9]
 #   Data_out[10]
 #   Data_out[11]
 #   Data_out[12]
 #   Data_out[13]
 #   Data_out[14]
 #   Data_out[15]
 #   ENB

 #
 # Core power and ground pads:
 # (These should be wired first by hand to ensure that
 # wide enough metal tracks are used)
 #

cpu_core_0/Vdd!
VDDcore/Vdd!

cpu_core_0/GND!
VSScore/GND!

 #
 # Input pads:
 #

cpu_core_0/Clock
Clock/Z

cpu_core_0/nReset
nReset/Z

cpu_core_0/Test
Test/Z

cpu_core_0/SDI
SDI/Z

cpu_core_0/nIRQ
nIRQ/Z

 #
 # Output pads:
 #

cpu_core_0/SDO
SDO/A

cpu_core_0/ALE
ALE/A

cpu_core_0/nME
nME/A

cpu_core_0/nOE
nOE/A

cpu_core_0/RnW
RnW/A

 #
 # Bidirectional pads:
 #

cpu_core_0/Data_in[0]
Data_0/ZI

cpu_core_0/Data_in[1]
Data_1/ZI

cpu_core_0/Data_in[2]
Data_2/ZI

cpu_core_0/Data_in[3]
Data_3/ZI

cpu_core_0/Data_in[4]
Data_4/ZI

cpu_core_0/Data_in[5]
Data_5/ZI

cpu_core_0/Data_in[6]
Data_6/ZI

cpu_core_0/Data_in[7]
Data_7/ZI

cpu_core_0/Data_in[8]
Data_8/ZI

cpu_core_0/Data_in[9]
Data_9/ZI

cpu_core_0/Data_in[10]
Data_10/ZI

cpu_core_0/Data_in[11]
Data_11/ZI

cpu_core_0/Data_in[12]
Data_12/ZI

cpu_core_0/Data_in[13]
Data_13/ZI

cpu_core_0/Data_in[14]
Data_14/ZI

cpu_core_0/Data_in[15]
Data_15/ZI


cpu_core_0/Data_out[0]
Data_0/A

cpu_core_0/Data_out[1]
Data_1/A

cpu_core_0/Data_out[2]
Data_2/A

cpu_core_0/Data_out[3]
Data_3/A

cpu_core_0/Data_out[4]
Data_4/A

cpu_core_0/Data_out[5]
Data_5/A

cpu_core_0/Data_out[6]
Data_6/A

cpu_core_0/Data_out[7]
Data_7/A

cpu_core_0/Data_out[8]
Data_8/A

cpu_core_0/Data_out[9]
Data_9/A

cpu_core_0/Data_out[10]
Data_10/A

cpu_core_0/Data_out[11]
Data_11/A

cpu_core_0/Data_out[12]
Data_12/A

cpu_core_0/Data_out[13]
Data_13/A

cpu_core_0/Data_out[14]
Data_14/A

cpu_core_0/Data_out[15]
Data_15/A

cpu_core_0/ENB
Data_0/EN
Data_1/EN
Data_2/EN
Data_3/EN
Data_4/EN
Data_5/EN
Data_6/EN
Data_7/EN
Data_8/EN
Data_9/EN
Data_10/EN
Data_11/EN
Data_12/EN
Data_13/EN
Data_14/EN
Data_15/EN

 #
 # End of netlist