Netlist File # Please note that the magic router is very fussy about the format of this # file. Spaces are important; any line beginning with a space is ignored; # if a space is included at the end of a terminal name the routing will fail. # Type "man -s 5 net" for further details. # cpu.net # # **** This version supports nIRQ pin **** # **** This version supports nWait pin **** # # This file assumes single sub-module cpu_core (instance name cpu_core_0) # It also assumes Data_in/_out signals use square brackets for index values # The required labels within cpu_core are: # Vdd! # GND! # Clock # nReset # Test # SDI # nIRQ # nWait # SDO # ALE # nME # nOE # RnW # Data_in[0] # Data_in[1] # Data_in[2] # Data_in[3] # Data_in[4] # Data_in[5] # Data_in[6] # Data_in[7] # Data_in[8] # Data_in[9] # Data_in[10] # Data_in[11] # Data_in[12] # Data_in[13] # Data_in[14] # Data_in[15] # Data_out[0] # Data_out[1] # Data_out[2] # Data_out[3] # Data_out[4] # Data_out[5] # Data_out[6] # Data_out[7] # Data_out[8] # Data_out[9] # Data_out[10] # Data_out[11] # Data_out[12] # Data_out[13] # Data_out[14] # Data_out[15] # ENB # # Core power and ground pads: # (These should be wired first by hand to ensure that # wide enough metal tracks are used) # cpu_core_0/Vdd! VDDcore/Vdd! cpu_core_0/GND! VSScore/GND! SDO/TM ALE/TM nME/TM nOE/TM RnW/TM Data_0/TM Data_1/TM Data_2/TM Data_3/TM Data_4/TM Data_5/TM Data_6/TM Data_7/TM Data_8/TM Data_9/TM Data_10/TM Data_11/TM Data_12/TM Data_13/TM Data_14/TM Data_15/TM SDO/TA ALE/TA nME/TA nOE/TA RnW/TA Data_0/TA Data_1/TA Data_2/TA Data_3/TA Data_4/TA Data_5/TA Data_6/TA Data_7/TA Data_8/TA Data_9/TA Data_10/TA Data_11/TA Data_12/TA Data_13/TA Data_14/TA Data_15/TA SDO/TEIN ALE/TEIN nME/TEIN nOE/TEIN RnW/TEIN Data_0/TEIN Data_1/TEIN Data_2/TEIN Data_3/TEIN Data_4/TEIN Data_5/TEIN Data_6/TEIN Data_7/TEIN Data_8/TEIN Data_9/TEIN Data_10/TEIN Data_11/TEIN Data_12/TEIN Data_13/TEIN Data_14/TEIN Data_15/TEIN # # Input pads: # cpu_core_0/Clock Clock/Z cpu_core_0/nReset nReset/Z cpu_core_0/Test Test/Z cpu_core_0/SDI SDI/Z cpu_core_0/nIRQ nIRQ/Z cpu_core_0/nWait nWait/Z # # Output pads: # cpu_core_0/SDO SDO/A cpu_core_0/ALE ALE/A cpu_core_0/nME nME/A cpu_core_0/nOE nOE/A cpu_core_0/RnW RnW/A # # Bidirectional pads: # cpu_core_0/Data_in[0] Data_0/ZI cpu_core_0/Data_in[1] Data_1/ZI cpu_core_0/Data_in[2] Data_2/ZI cpu_core_0/Data_in[3] Data_3/ZI cpu_core_0/Data_in[4] Data_4/ZI cpu_core_0/Data_in[5] Data_5/ZI cpu_core_0/Data_in[6] Data_6/ZI cpu_core_0/Data_in[7] Data_7/ZI cpu_core_0/Data_in[8] Data_8/ZI cpu_core_0/Data_in[9] Data_9/ZI cpu_core_0/Data_in[10] Data_10/ZI cpu_core_0/Data_in[11] Data_11/ZI cpu_core_0/Data_in[12] Data_12/ZI cpu_core_0/Data_in[13] Data_13/ZI cpu_core_0/Data_in[14] Data_14/ZI cpu_core_0/Data_in[15] Data_15/ZI cpu_core_0/Data_out[0] Data_0/A cpu_core_0/Data_out[1] Data_1/A cpu_core_0/Data_out[2] Data_2/A cpu_core_0/Data_out[3] Data_3/A cpu_core_0/Data_out[4] Data_4/A cpu_core_0/Data_out[5] Data_5/A cpu_core_0/Data_out[6] Data_6/A cpu_core_0/Data_out[7] Data_7/A cpu_core_0/Data_out[8] Data_8/A cpu_core_0/Data_out[9] Data_9/A cpu_core_0/Data_out[10] Data_10/A cpu_core_0/Data_out[11] Data_11/A cpu_core_0/Data_out[12] Data_12/A cpu_core_0/Data_out[13] Data_13/A cpu_core_0/Data_out[14] Data_14/A cpu_core_0/Data_out[15] Data_15/A cpu_core_0/ENB Data_0/EIN Data_1/EIN Data_2/EIN Data_3/EIN Data_4/EIN Data_5/EIN Data_6/EIN Data_7/EIN Data_8/EIN Data_9/EIN Data_10/EIN Data_11/EIN Data_12/EIN Data_13/EIN Data_14/EIN Data_15/EIN # # End of netlist