Cross Simulation (Interim Hand-in)

Deliverables

• All magic files should be placed in the directory: ~/design/fcde/magic

  The files will be located in the two sub-directories as detailed in the original specification:

  • cell_lib

    containing the cells of your cell library.

  • design

    containing the hierarchical cells created for this exercise.

    The top level cell for this submission should be datapath.mag.

  CHECK

     cd ~/design/fcde/magic/design
     magic datapath
  

  Here you should be able to open the datapath cell and view the full hierarchy. If you select the datapath cell and type :expand you will be warned if any cells are missing or if timestamps are wrong. If the files are up to date you will be able to exit from magic without being prompted to save updated cells.

     fcde_magic_tarball datapath
  

  This command is used by the handin script to create a tar file including all of the magic files. Testing here is more rigorous, including checks for misplaced files (e.g. leaf cells in the design directory) and files that have been corrupted by DOS programs such as PC mailers.

• All SystemVerilog files should be placed in the directory: ~/design/fcde/verilog

  This directory should contain all files necessary for HDL simulation and modelling.

  In addition to the simulate script, this directory will contain five sub directories (other sub-directories such as structural or extracted may exist but will not be considered part of this submission):

  • system

    This sub-directory contains the system HDL files, these should be the same as those initially provided.

  • mixed

    This sub-directory contains a mix of behavioural models and extracted netlists for your processor.

    • cpu_core.sv

      cpu_core module - joins control & datapath

    • control.sv

      control module - generates control signals

    • opcodes.svh

      package file for your opcodes and other definitions

    • options.sv

      include file for simulation options

    • monitor.sv

      contains signal and function definitions helpful for monitoring your simulation

      also contains code that is responsible for termination of the simulation

    • system.tcl

      NC-Verilog simvision control file for your system

    • system.fig (optional)

      If present, an xfig picture file like this may be used to provide an advanced view of the processor in a simvision register window. This is the technique used in the example processor simulations.

    • datapath.sv

      header file for magic datapath module

    • datapath.svnet

      netlist file for magic datapath module

  • behavioural

    This sub-directory contains a complete behavioural model of your processor.

    The files in this directory may be largely unchanged from those submitted in the previous handin except where updates have been made in oder to keep the behavioural model in sync with the cross simulation.

    Note that the control.sv and opcodes.svh files in this directory should be identical to those in the mixed directory.

  • programs

    This sub-directory contains the program files for each of a number of test programs for your processor.

    Eventually this directory will contain the multiply, factorial and random program files required in the specification.

    At this stage only the files for the multiply program are required (unless your processor supports interrupts):

    • multiply.sv, multiply.asm, multiply.hex and multiply.txt

    The descriptions and specifications for these files were provided for the previous handin. The only change is that the multiply.txt file must be provided for this handin (whereas it was optional for the previous handin). Conversely, the multiply.sv file may be omitted from this handin where the multiply.hex and multiply.txt files are automatically generated from multiply.asm by an assembler program.

    If your design supports interrupts, you will also have to include files for the interrupt program in this directory:

    • interrupt.sv, interrupt.asm, interrupt.hex and interrupt.txt

  CHECK

     cd ~/design/fcde/verilog
     ./simulate mixed programs/multiply.hex 200 +define+switch_value=2569
  

  This should multiply 9 by 10 and put the result on the LEDs. Here I have set the simulation time to 200 clock cycles; you will need to modify this for your simulation. When you perform the handin preparation it will ask you for the simulation time.

  You should also confirm that the same result is gained from the behavioural simulation:

     ./simulate behavioural programs/multiply.hex 200 +define+switch_value=2569
  

  In addition, simulations for the interrupt program are required if your processor supports interrupts:

     ./simulate behavioural programs/interrupt.sv programs/serial_data.hex
     ./simulate mixed programs/interrupt.sv programs/serial_data.hex
  

Hand-in Script

• Run the prepare_fcde command:

     prepare_fcde mixed
  

  or, if your design supports interrupts, use this version of the command:

     prepare_fcde -interrupt mixed
  

  This will run some tests and then copy your design files into a "tar" format archive file "handin.tar". You can then submit this file via the handin system.

  It is suggested that you try out the handin script early (several days before the deadline). If your design fails the tests carried out in the handin script, it will fail automated testing.