Electronic Hand-in Procedure for Final Design

Deliverables

• All magic files should be placed in the directory: ~/design/fcde/magic

  The files will be located in the two sub-directories as detailed in the original specification:

  • cell_lib

    containing the cells of your cell library.

  • design

    containing the hierarchical cells created for this exercise.

    The top level cell should be cpu.mag which should include the cpu_core and all the cells from the pad ring.

  CHECK

     cd ~/design/fcde/magic/design
     magic cpu
  

  Here you should be able to open the cpu cell and view the whole design. If you select the full design and type :expand you will be warned if any cells are missing or if timestamps are wrong. If you have copied the files correctly you will be able to exit from magic without being prompted to save updated cells.

     fcde_magic_tarball cpu
  

  This command is used by the handin script to create a tar file including all of the magic files. Testing here is more rigorous, including checks for misplaced files (e.g. leaf cells in the design directory) and files that have been corrupted by DOS programs such as PC mailers.

• All SystemVerilog files should be placed in the directory: ~/design/fcde/verilog

  This directory should contain all files necessary for HDL simulation and modelling.

  In addition to the simulate script, this directory will contain five sub directories (other sub-directories such as mixed or gate_level may exist but will not be considered part of this submission):

  • system

    This sub-directory contains the system HDL files as provided to you.

  • behavioural

    This sub-directory contains the high level SystemVerilog HDL model of the processor. This is likely to differ from the behavioural model submitted previously as you will have developed your design in the light of your experiences with circuit design, layout and in particular SystemVerilog synthesis.

    The top level cell should be cpu_core.sv

  • extracted

    This sub-directory contains the structural SystemVerilog HDL model of your processor as extracted from your magic files.

    The top level cell should be cpu.sv which will reference the circuit description from cpu.svnet.

    This directory will also contain the usual support files: opcodes.sv, monitor.sv, system.tcl, and system.fig(optional).

    The final file in this directory is a special stimulus file, stimulus.sv, which provides a simple scan path test.

  • programs

    This sub-directory contains the program files for each of a number of test programs for your processor.

    The three programs required for this handin are multiply, factorial and random as detailed in the programs specification.

    The files required in this directory are:

    • multiply.sv, multiply.asm, multiply.hex and multiply.txt

    • factorial.sv, factorial.asm, factorial.hex and factorial.txt

    • random.sv, random.asm, random.hex and random.txt

    In addition, files for the interrupt program are required if your processor supports interrupts:

    • interrupt.sv, interrupt.asm, interrupt.hex and interrupt.txt

    The file formats for these files are described in the documentation for the behavioural handin.

    Note that the <prog>.sv files may be omitted from this handin where the <prog>.hex and <prog>.txt files are automatically generated from <prog>.asm by an assembler program.

  CHECK

     cd ~/design/fcde/verilog
     ./simulate behavioural programs/multiply.hex +define+switch_value=1798
     ./simulate behavioural programs/factorial.hex +define+switch_value=7
     ./simulate behavioural programs/random.hex +define+switch_value=303
     ./simulate extracted programs/multiply.hex +define+switch_value=1798
     ./simulate extracted programs/factorial.hex +define+switch_value=3
     ./simulate extracted programs/random.hex +define+switch_value=303
  

  Here you should be able to run three different simulations on each of the SystemVerilog descriptions. Note that the switch value is used to specify either the number for which we want the factorial or the seed for the random number generator (The extracted simulation for factorial uses a smaller number since the transistor level simulation is much slower). Results are written to the LEDs so that they can be easily identified.

  In addition, simulations for the interrupt program are required if your processor supports interrupts:

     ./simulate behavioural programs/interrupt.hex programs/serial_data.hex
     ./simulate extracted programs/interrupt.hex programs/serial_data.hex
  

  The commands required for other simulations (e.g. a simple scan path test) should be documented in your report.

• Assembler files?

  Most years at least one team implements an assembler for their processor. If you have an assembler, you should place all relevant files in ~/design/fcde/verilog/assembler (including a README file to explain how to use the assembler). If you have no assembler then you should not create the assembler directory.

Hand-in Script

• Run the command: prepare_fcde final

  This will run some tests and then copy your design files into a "tar" format archive file "handin.tar". You can then submit this file via the handin system.

  It is suggested that you try out the handin script early (several days before the deadline). If your design fails the tests carried out in the handin script, it will fail automated testing.