Simple Processor - Example 1

A very simple single bus processor has been designed using Verilog Hardware Description Language.

The processor has a 16-bit data path and a 12-bit address space.

Each instruction is one word (16-bits) wide and consists of a 4-bit opcode and a 12-bit address operand:

The following instructions are supported:

Instruction	Opcode	Operation

  NOP		  0	No Operation
  JMP		  1	PC <= address
  JMPZ		  2	if (Z==1) then PC <= address
  JMPNZ		  3	if (Z==0) then PC <= address
  LDA		  4	ACC <= mem(address)
  ADD		  5	ACC <= ACC + mem(address)
  SUB		  6	ACC <= ACC - mem(address)
  AND		  7	ACC <= ACC & mem(address)
  OR		  8	ACC <= ACC | mem(address)
  NOT		  9	ACC <= ~ACC
  LSL		  10	ACC <= ACC << 1
  LSR		  11	ACC <= ACC >> 1
  STA		  15	mem(address) <= ACC

For this exercise you must investigate the behaviour of the design using the Verilog XL simulator. This advanced digital simulator allows you to track bus and register values as the simulated machine executes a machine code program.

Running the simulation

• Initialise your environment using the following command:

  	init_fcde_example1
  

  this command will
  • create a working directory ~/design/verilog/processor/example1
  • copy the files library/processor.sv, library/control.sv, library/datapath.sv, library/alu.sv, library/memory.sv, library/opcodes.svh, library/monitor.sv, programs/multiply.sv and system.sv to that directory
  • open a new xterm window set to the correct directory (you will use this new xterm for the rest of the exercise)

• Simple Code

  • The following assembly language instructions are coded in the file library/memory.sv:

            LDA    varX
    .loop   SUB   #1
            JMPZ  .done
            STA   varY
            ADD   varX
            STA   varX
            LDA   varY
            JMP   .loop
    .done   LDA   varX
            JMP   .end
    
    .end    JMP   .end
    

    where
    • varX is a variable stored at address 22 (varX has an initial value of 7)
    • varY is a variable stored at address 23
    • #1 is the constant value 1 stored at address 21

  • Using the following command, you can investigate the operation of the processor:

      ncverilog -sv +gui +ncaccess+r +tcl+system.tcl -y library +libext+.sv +incdir+library library/opcodes.svh system.sv
    

    There is a simulate script in the directory that can save some typing:

      ./simulate
    

    In addition to a waves window, there are two registers windows. One shows a view of the datapath architecture annotated with the values of registers and signals (this is automatically generated from an xfig file called system.fig). The other shows the content of the memory.

By stepping forwards and backwards through the simulation you should be able to observe the flow of the program listed above, including the update of memory locations and registers.

Which registers are updated during the Fetch state? Which registers are updated during the Execute state?

Can you follow the update of the Accumulator (ACC), based on the ALU function and the current state of ACC and DataBus?

For each of the first 20 clock cycles, you should record the values of the registers and memory variables. Then run through the same 20 clock cycles again - can you predict the update of registers and memory based on the information shown by the simulation?

Follow the simulation to it's conclusion - can you see what it is doing?

Multiplication Code

• The following assembly language instructions are coded in the file programs/multiply.sv:

          LDA   #0
          STA   varP
          LDA   varB
  .loop   AND   #1
          JMPZ  .noadd
          LDA   varP
          ADD   varA
          STA   varP
  .noadd  LDA   varA
          LSL
          STA   varA
          LDA   varB
          LSR
          STA   varB
          JMPNZ .loop
          JMP   .end
  
  .end    JMP   .end
  

  where
  • varA is a variable stored at address 22 (varA has an initial value of 5)
  • varB is a variable stored at address 23 (varB has an initial value of 5)
  • varP is a variable stored at address 24
  • #0 is the constant value 0 stored at address 20
  • #1 is the constant value 1 stored at address 21

• Use the simulator to investigate the execution of this code.

    ./simulate programs/multiply.sv
  

  Follow the execution of the code from start to finish. Convince yourself that the operation being performed is a simple software multiply with no error checking.

  Use a text editor to change the initial values of varA and varB defined in programs/multiply.sv to 343 and 9 respectively. Re-run the simulation. What answer is calculated? How many clock cycles does the operation take? Is the answer correct?

  Now set the initial values to varA=9 and varB=343. Re-run the simulation. What answer is calculated? How many clock cycles does the operation take? Is the answer correct?

  Now set the initial values to varA=343 and varB=343. Re-run the simulation. What answer is calculated? How many clock cycles does the operation take? Is the answer correct?

  Analyse the results that you have obtained. Can you explain any unusual findings?