The simulation environment for the VLSI Design Project consists of a number of SystemVerilog files which model a basic computer system built around the microprocessor under test:
The system employs a bus structure with the microprocessor as bus master and memory and I/O devices as bus slaves.
From the point of view of the microprocessor bus master, the address is multiplexed, with address and data sharing the 16-bit Data bus:
The address latch within the bus interconnect serves to de-multiplex the bus such that the slaves see separate address and data signals:
note that the ME (not memory enable) line from the microprocessor bus master is gated in the Address Decoder to provide separate CE (not chip enable) lines to each slave device.
SystemVerilog supports an interface construct which allows us to group all the wires for the interconnect together with some of the associated logic.
The diagram below is a block diagram for one possible implementation of the system based around a SystemVerilog interface rather than a set of individual wires:
In this example the connections to the interface are made through the interface modports:
Each modport defines the sub-set of the bus connections that will connect to the module along with the direction (input, output or inout) from the point of view of the connected module. Thus the definition for the Master modport is:
modport Master (
inout Data,
output ALE, nME, nOE, RnW,
input nIRQ, nWait
);
There is no Address Latch in the above diagram because the functionality of the address latch is included within the interface.
The complete SystemVerilog code for this simple example interface can be found in:
simple_interface.sv
The interface used in the simulation environment is slightly more complex:
e.g. a pair of assertions exist to ensure that the address is stable on the Data bus before and after the falling edge of ALE signal.
The SystemVerilog code for the interface can be found in:
demux_bus.sv
The hierarchy of the design is defined within the top-level module and testbench file which instances the demux_bus interface along with sub-modules for the bus master, bus slaves and the address decoder:
system.sv
The address decoder provides the device select signals for all of the slaves.
decoder.sv
The external memory and I/O supports a number of different configurations. The default (reduced address map) configuration includes:
A behavioural model (not synthesizable) of the RAM module can be found in the SystemVerilog file:
ram.sv
The RAM is used to store program code and data. Initially the RAM values are undefined but 1 ns after the beginning of the simulation, the program code is loaded from a .hex file.
The processor may read and write any location within the RAM.
A behavioural model (not synthesizable) of the switches module can be found in the SystemVerilog file:
io_switches.sv
The address of the switches is a read-only location. The processor can read from the switches but must not attempt to write to the switches.
A behavioural model (not synthesizable) of the LEDs module can be found in the SystemVerilog file:
io_leds.sv
The address of the LEDs is a write-only location. The processor can write to the LEDs but must not attempt to read from the LEDs.
io_serial.sv
The io_serial module simulates a dummy serial interface and is the main source of interrupts for processors which support interrupts.
io_timer.sv
The io_timer module simulates a real-time clock chip and can act as an alternative source of interrupts during processor development. This module is only visible to the processor if the full address map configuration is selected.
Top level module for the microprocessor
cpu.sv
The Initialise your environment using the following command:
Simulation
init_fcde_example
this command will
Using the following command, you can investigate the operation of the processor:
./simulate <model_dir> <program_file> <num_clocks>
To run an alternative program you can try:
./simulate example/new_prog.hexwhere example/new_prog.hex is a new hex format file that you have created.
or
./simulate example/new_program.svwhere example/new_program.sv is a new SystemVerilog program file that you have created. In this case the simulation will first assemble a new example/new_program.hex hex format file and then load the program from here into the ram for execution.
+define+switch_value=n
This option allows an initial input value to be specified for the switches.
+define+full_address_map
or
+define+reduced_address_map
These options allows either the standard (reduced_address_map) or the alternate (full_address_map) configuration to be specified for the system (your processor should be able to cope with either configuration).
+define+ram_access_time=t
+define+switch_access_time=t
+define+led_access_time=t
+define+serial_access_time=t
+define+timer_access_time=t
These options allow the access times for the individual slaves to be customized.
+define+special_stimulus
This option indicates that the simulation should use the advanced stimulus information found in the stimulus.sv file.
+define+special_monitor
This option indicates that the simulation should use the advanced monitoring information found in the monitor.sv file.
In addition there is an options.sv file which is included by a number of the sytem modules and which defines marcos to control simulation options:
The simulate script may also be called with options:
./simulate +define+switch_value=8 ./simulate +define+special_stimulus ./simulate +define+special_monitor ./simulate +define+ram_access_time=2usNote that the +define+special_monitor option has no effect since it is set as the default in the options.sv file.
For your own HDL design, copy the example files to a new directory:
cp -r example mydesignThen edit the files in the new directory to reflect your design. You can simulate your design using:
./simulate mydesignSince you are likely to have more than one test program, you can specify the program file on the command line:
./simulate mydesign programs/myprog1.svNote that if you need to include options they should occur after the design directory and program file specification:
./simulate mydesign programs/myprog1.sv +define+switch_value=5
Iain McNally
23-3-2012