VLSI Design Project - Documentation
Division of Labour
Please fill in for all tasks completed.
The numbers in each row should add up to 100%
Ensure that all team members sign the form.
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Task
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Percentage Effort on each Task
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ECSID:
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_________
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_________
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_________
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_________
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_________
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1
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Initial Design
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2
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Verilog Behavioural Model
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3
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Multiply Program
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4
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Magic Datapath
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5
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Verilog Cross Simulation
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6
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Control Unit Synthesis
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7
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Magic Control Unit
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8
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Final Floorplanning, Placement and Routing
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9
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Factorial Program
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10
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Random Program
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11
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Verilog Final Simulations and Cadence DRC
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12
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Assembler (if done)
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13
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Programmer's Guide Documentation
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14
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Final Report
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OVERALL EFFORT
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Signature:
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