VLSI Design Project 2009/2010

Full Custom Design Exercise

Aim

The aim of this exercise is to design a novel microprocessor unit in full custom 0.35um CMOS, using Magic for layout and Verilog for simulation. In addition, L-Edit may optionally be used for automated place and route while Cadence will be used for design sign-off procedures. A specification for the microprocessor unit is attached.

Design Style

For this exercise it is required that you design using a standard cell library (which you have created). All designs must be synchronous to the rising edge of a global clock. All designs should have a single active-low reset line to clear all internal flip-flops. All designs should use scan path testability for the isolation of errors following fabrication, and to help in the production of test vectors.

Internal Tri-state Buses

Although your design will have an external tri-state bus, there is in fact no requirement for an internal tri-state bus. Should you decide to use such a bus, your cell library includes a tri-state buffer for this purpose. Note that an internal tri-state bus should be driven by exactly one driver in every cycle. This should be true even during scan path testing when the controller may enter unexpected states.

Design and Simulation with Verilog HDL

As well as the simulation of transistor netlists, Verilog can be used in the specification and initial simulation of your design using a behavioural description. Verilog will also allow you to perform a system simulation using a transistor netlist for your processor and behavioural models for the other system components. For the purpose of pre-layout and post-layout simulation I have prepared the a number of Verilog system files which have behavioural models for the system components except the CPU itself.

To help you get started with pre-layout simulation, I have prepared further Verilog example files which include the behavioural model for a simple CPU. A simple program is loaded into RAM which illustrates the processor operation. These files should provide the basis for a behavioural model of your CPU.

Further details of this example CPU are available on the Web.

File Location

To avoid problems later in the design process, files should be located as follows:

Cell Library
```
    ~/design/fcde/magic/cell_lib
```
This directory should contain the cell library files previously designed.
Magic Design Files
```
    ~/design/fcde/magic/design
```
This directory should contain the design files for this exercise. It should not contain any library cells or pad cells. You will need a special .magic file in this directory to allow your library cells (from the cell_lib directory) and also standard pad cells (from a central read-only location) to be properly referenced.
Verilog Behavioural Model
```
    ~/design/fcde/verilog/behavioural
```
This directory should contain the verilog files that make up the behavioural model for your design.
Test Programs
```
    ~/design/fcde/verilog/programs
```
This directory should contain the verilog "rom" files that contain the programs to test your design.

A script has been written to create these directories, to add the .magic file and to include the pre-defined pad library cells. Simply type

    init_fcde_directories

Groups

The design exercise is to be tackled in groups of between three and five. The group may divide the work as it sees fit, but all members of the group should be kept active at all stages of the project.

Deliverables

The deliverables for the project are:

an initial design document
a high level Verilog HDL model of the processor.
a Verilog cross simulation using an extracted datapath.
the chip design itself.
a programmer's guide
scan path test vectors and example programs to illustrate design functionality.
a single project report from each group.

Further details of these deliverables are (or will be) available on the Web.

Marking & Report Writing

Marks will be awarded for the following:

The Design of the instruction set and its mapping to the chosen architecture. To achieve a good mark for the design phase it will be necessary to show that your design has been influenced by your independent research and/or original thinking.
The Design of the circuit and its use of hierarchy. Of particular interest is the re-use of blocks to reduce layout time.
The implementation of the design onto silicon along with its proven functionality.
The design of good test vectors which test the different features of the design.

The report should clearly document all of the above, further marks will be available for the quality of the documentation.

An appendix to the report should indicate how the project was managed and how the tasks were divided amongst the members of the group. This will aid in the adjustment of marks for the different group members.

This is essentially a group project, all group members must share responsibility for the results, comments such as the following will not be well received:

``I only designed it. If it doesn't work then it's his fault, he was responsible for testing.''

``She didn't understand the interface we agreed upon.''

Additional Documentation

Information on layout, simulation and DRC of Magic designs can be found on the CAD Tools and Techniques home page.
Information on simulation and hardware modelling with Verilog can be found on the same CAD Tools and Techniques home page.
The full Magic Tutorial is always worth looking at, having lots of tips for advanced Magic usage.
Cadence and Verilog manuals are available on-line via the cdnshelp help viewer.

Iain McNally

1-2-2010