Teams and Declaration of Specialisms


Week 4 Week 5 Week 6 Week 7 Week 9 Week 10 Week 12
Team Name Research Report

20 Feb
4 pm

 Draft Design

21 Feb
12 noon

 Initial Design

27 Feb
4 pm

 Behavioural Model
(4 instructions)

28 Feb
2 pm

 Behavioural Model

6 Mar
4 pm

 Basic Datapath Simulation (ALU + Registers)

7 Mar
12 noon

 extra

8 Mar
4 pm

 Cross Simulation

13 Mar
4 pm

 Placed and Routed Control Unit Simulation

14 Mar
12 noon 4pm

 Placed and Routed Pad Ring Simulation

25 Apr
12 noon

 Design Submission

3 May
4 pm

 Project Report

14 May
4 pm
Instruction
Set		 Datapath
Diagram		 Instruction
Set		 Datapath
Diagram		 Verilog
Model		 Multiplication
Code		 Magic
Datapath		 Verilog
Control		 Design
Files		 Programmer's
Guide
A1 ja9g08 1 ALL x x x x ALL
A1 mas2e12 4 ALL x x x x ALL
A1 oaa1c12 3 ALL x x x ALL
A1 af3g12 2 ALL x x x ALL
A2 lz9g12 1 ALL x x x ALL
A2 ns1e12 4 ALL x x x ALL
A2 bz3g12 3 ALL x x x ALL
A2 rc6e12 2 ALL x x ALL
A2 xz5e12 5 ALL x x x ALL
A3 qz1g12 3 ALL x x x ALL
A3 wz3e12 2 ALL x x x x ALL
A3 xy5e12 1 ALL x x x x ALL
A3 yy6g12 4 ALL x x x ALL
A4 ddjp1g12 1 ALL x x x ALL
A4 ds2g12 3 ALL x x x ALL
A4 mvm1e12 4 ALL x x x x ALL
A4 skpr1g12 2 ALL x x x x ALL
B1 jy3e12 2 ALL x x ALL
B1 tz1g12 5 ALL x x x ALL
B1 yl5g12 4 ALL x x x ALL
B1 yz15e12 3 ALL x x x x ALL
B1 zz14g12 1 ALL x x ALL
B2 mw1g09 3 ALL x x x ALL
B2 rcjg1g09 4 ALL x x x x ALL
B2 sa16g08 1 ALL x x x x ALL
B2 sh31g09 2 ALL x x x ALL
B3 mm4g12 4 ALL x x x ALL
B3 gl2e12 2 ALL x x x ALL
B3 cy2e12 1 ALL x x x ALL
B3 sc6e12 5 ALL x x x ALL
B3 bl3e12 3 ALL x x ALL