| Week 3 | Week 4 | Week 5 | Week 6 | Week 10 | Week 12 | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Team | Name | Research Report
15 Feb
|
Draft Design
16 Feb
|
Initial Design
22 Feb
|
Behavioural Model
(4 instructions) 23 Feb
|
Behavioural Model
29 Feb
|
Basic Datapath Simulation (ALU + Registers)
1 Mar
|
extra
2 Mar
|
Cross Simulation
7 Mar
|
Placed and Routed Control Unit Simulation
8 Mar
|
Design Submission
4 May
|
Project Report
15 May
|
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| Instruction
Set |
Datapath
Diagram |
Instruction
Set |
Datapath
Diagram |
Verilog
Model |
Multiplication
Code |
Magic
Datapath |
Verilog
Control |
Design
Files |
Programmer's
Guide |
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| ALL | ALL | |||||||||||||||||
| ALL | ALL | |||||||||||||||||
| ALL | ALL | |||||||||||||||||
| ALL | ALL | |||||||||||||||||
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