|
|
Week 3 |
Week 4 |
Week 5 |
Week 6 |
Week 10 |
Week 12 |
| Team |
Name |
Research Report
15 Feb
4 pm |
Draft Design
16 Feb
12 noon |
Initial Design
22 Feb
4 pm |
Behavioural Model
(4 instructions)
23 Feb
2 pm |
Behavioural Model
29 Feb
4 pm |
Basic Datapath Simulation (ALU + Registers)
1 Mar
12 noon |
extra
2 Mar
4 pm |
Cross Simulation
7 Mar
4 pm |
Placed and Routed Control Unit Simulation
8 Mar
12 noon |
Design Submission
4 May
4 pm |
Project Report
15 May
4 pm |
Instruction
Set |
Datapath
Diagram |
Instruction
Set |
Datapath
Diagram |
Verilog
Model |
Multiplication
Code |
Magic
Datapath |
Verilog
Control |
Design
Files |
Programmer's
Guide |