lappend search_path ../src
analyze -format sv "opcodes.svh cpu.sv cpu_core.sv control.sv datapath.sv alu.sv"
elaborate cpu
check_design unresolved


source ../constraints/design.sdc

check_timing > ../reports/check_timing.rpt


ungroup -all


compile_ultra -exact_map

set_fix_multiport_nets -all [all_designs]

change_names -rules verilog -hierarchy -verbose




report_timing > ../reports/synth_timing.rpt

report_area > ../reports/synth_area.rpt

report_qor

write -f verilog -output ../gate_level/cpu.v

write_sdf ../gate_level/cpu.sdf

exit