Design Exercise 4 - Preparation for Handin

This document discusses the operation of the script that checks design exercise 4 and prepares the handin.tar file for electronic submission:

    prepare_dicd desex4

Before creating the handin.tar file, basic file checks, more file checks and simulation checks are performed:

Basic File Checks

In each case the script will check that the file exists and has the correct format (e.g. it checks that scandtype.mag exists and is a magic file with technology c035u).

Checks for Magic files in ~/design/magic/c035u/cell_lib directory
- scandtype.mag
- scanreg.mag
- trisbuf.mag
- buffer.mag
- mux2.mag
- fulladder.mag
- xor2.mag
- inv.mag
- nand2.mag
- nand3.mag
- nor2.mag
- nor3.mag
- halfadder.mag
- and2.mag
- or2.mag
- nand4.mag
- tielow.mag
- tiehigh.mag
- rowcrosser.mag
- leftbuf.mag
- rightend.mag
Checks for Magic files in ~/design/magic/c035u/bitslice directory
- bitslice.mag
- datapath.mag
Checks for SystemVerilog files in ~/design/magic/c035u/bitslice directory
- bitslice.sv
- bitslice_stim.sv
- datapath.sv
- datapath_stim.sv
- control.sv
- control_stim.sv
- divider.sv
- divider_stim.sv
- divider.tcl
Checks for SystemVerilog netlist files in ~/design/magic/c035u/bitslice directory
- bitslice.vnet
- datapath.vnet

More File Checks

Checks that Magic leaf cells contain no hierarchy
- scandtype
- scanreg
- trisbuf
- buffer
- mux2
- fulladder
- xor2
- inv
- nand2
- nand3
- nor2
- nor3
- halfadder
- and2
- or2
- nand4
- tielow
- tiehigh
- rowcrosser
- leftbuf
- rightend
Checks hierarchy for the bitslice cell
The bitslice cell should instance only cells from the list of leaf cells above.
Checks hierarchy for the datapath cell
The datapath cell should instance only the bitslice cell.

Simulation checks

Simple division check
This test uses your system to perform a single division calculation. It will observe the result but make no judgement as to whether the answer is correct.
The simulation will fail if the inputs and outputs for the divider.sv file are not as specified below:
```
    input [7:0] Operand1, Operand2;
    input Req;
    input Clock, nReset;
    output [7:0] Quotient, Remainder;
    output Done;
```
Simple bitslice scan path test
This test places a one clock cycle pulse on the Scan Data In (SDI) input of the bitslice module and checks to see that there is a corresponding pulse on the Scan Data Out (SDO) output. For a design with 5 dtypes/registers, the SDO pulse should be produced 5 cycles after the SDI pulse indicating that the scan path is correctly wired.
The simulation will fail if the inputs and outputs for the bitslice.sv do not include those which should be common to all bitslice designs:
```
    input Operand1, Operand2;
    input Clock, nReset, Test, SDI;
    output Quotient, Remainder;
    output SDO;
```
Simple datapath scan path test
This test places a one clock cycle pulse on the Scan Data In (SDI) input of the datapath module and checks to see that there is a corresponding pulse on the Scan Data Out (SDO) output. For a design with 40 dtypes/registers, the SDO pulse should be produced 40 cycles after the SDI pulse indicating that the scan path is correctly wired.
If you have opted for a type 1 datapath, the simulation will fail if the inputs and outputs for the datapath.sv file are not as specified below:
```
    input [7:0] Operand1, Operand2;
    input Subtract, Increment;
    input EnableD, EnableACC, EnableOp1, EnableOp2;
    input LoadD, LoadR, LoadC, LoadQ, LoadACC;
    input Clock, nReset, Test, SDI;
    output [7:0] Quotient, Remainder;
    output nBorrow, Overflow;
    output SDO;
```
If you have opted for an alternative datapath then you will have different control signals and different feedback signals. In this case the simulation will only check for the signals that it knows should be common to all datapath designs.
For a type 2 datapath these are:
```
    input [7:0] Operand1, Operand2;
    input Clock, nReset, Test, SDI;
    input ShiftIn;
    output [7:0] Quotient, Remainder;
    output nBorrow, nZ;
    output SDO;
```
For a type 3 datapath these are:
```
    input [7:0] Operand1, Operand2;
    input Clock, nReset, Test, SDI;
    output [7:0] Quotient, Remainder;
    output SDO;
```

Handin

For a handin.tar file to be automatically created all the file checks must succeed (basic file checks and more file checks).

Although a design that doesn't pass the simulation checks does not meet the specification, such a design will still create a handin.tar file. This allows students who are experiencing difficulties, to make a submission based on their current design and then to get on with the documentation.

The more organized students will use the script early to help them with their debugging. Only once they are happy with their designs will they consider submitting the handin.tar file.

Iain McNally

28-11-2013